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Part II CST SoC D/M Slide Pack 6 (ESL)
Architectural Exploration using ESL Modelling
SystemC: Hardware Modelling Library Overview
Example (Counter)
ESL Flow Model: Avoiding ISS/RTL overheads using native calls.
Using C Preprocessor to Adapt Firmware
Transactional-Level Modelling (TLM)
Example Protocol: 4/P Handshake at net-level and TLM level.
General ESL Interactions with Shortcuts Illustrated
Mixing modelling styles: 4/P net-level to TLM transactors.
Transactor Configurations
Example of non-blocking coding style:
TLM 1.0 Form Example.
ESL TLM in SystemC: TLM 2.0
TLM in SystemC: TLM 2.0
TLM 2.0 - Tiny Example - Memory SRAM Model
TLM 2.0 Socket Types
CSharp Implementation
Timed Transactions: Adding delays to TLM calls.
TLM Modelling: Adding Approximate Timing Annotations
TLM - Measuring Utilisation and Modelling Contention
Replacing Queues With Delay Estimates
Instruction Set Simulator (ISS)
Typical ISS setup with Loose Timing (Temporal Decoupling)
Power Estimation: RTL versus ESL
RTL Operating Frequency and Power Estimation
Gold standard: Power Estimation using Simulation Post Layout
RTL Power Estimation by Static Analysis (ie Without Simulation)
Typical macroscopic performance equations: SRAM example.
Typical macroscopic performance equations: DRAM example.
Rent's Rule Estimate of Wire Length
Macroscopic Phase/Mode Power Estimation Formula
Spreadsheet-based Energy Accounting
Transactional Energy Modelling
TLM POWER 3 library for SystemC: SRAM example
TLM POWER 3 Report File Example
sPEEDO Energy Interface
Higher-Level Simulation - Virtual Platforms