- PhD Student under the supervision of Peter Sewell at the Computer Laboratory, University of Cambridge since October 2014, working on the semantics of concurrent ARM and POWER programs.
- 2013-2014: MPhil in Computer Science at the University of Cambridge. MPhil thesis supervisor: Magnus Myreen. Thesis title: “Synthesis of impure ML from monadic HOL functions.”
- 2010-2013: BSc in Computer Science at TU Dortmund. supervisor: Thomas Schwentick. Thesis title: “Visibly Pushdown Automata: Algorithmen und Abschlusseigenschaften.”
Office FS20, Computer Laboratory
15 JJ Thomson Avenue
Cambridge, CB3 0FD, UK
- ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS. A. Armstrong, T. Bauereiss, B. Campbell, A. Reid, K. E. Gray, R. M. Norton, P. Mundkur, M. Wassell, J. French, C. Pulte, S. Flur, I. Stark, N. Krishnaswami, and P. Sewell, in POPL 2019.
- Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and Operational Models for ARMv8. C. Pulte, S. Flur, W. Deacon, J. French, S. Sarkar, and P. Sewell, in POPL 2018.
- Mixed-size Concurrency: ARM, POWER, C/C++11, and SC. S. Flur, S. Sarkar, C. Pulte, K. Nienhuis, L. Maranget, K. E. Gray, A. Sezgin, M. Batty, and P. Sewell, in POPL 2017.
- Modelling the ARMv8 Architecture, Operationally: Concurrency and ISA. S. Flur, K. E. Gray, C. Pulte, S. Sarkar, A. Sezgin, L. Maranget, W. Deacon, and P. Sewell, in POPL 2016.
- An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors, K. E. Gray, G. Kerneis, D. P. Mulligan. C. Pulte, S. Sarkar, and P. Sewell, in MICRO 2015.