Sail is a language for expressing multiprocessor ISA descriptions. It is currently being used for ARM, RISC-V, CHERI, IBM Power, MIPS, and x86 descriptions, varying from full definitions to core user-mode fragments.

The Sail source and documentation, and some of those models, are available in a public github repository.




This work was partially supported by EPSRC grant EP/K008528/1 REMS: Rigorous Engineering for Mainstream Systems, an ARM iCASE award, and EPSRC IAA KTF funding. Approved for public release; distribution is unlimited. This research is sponsored by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory (AFRL), under contracts FA8750-10-C-0237 ("CTSRD") and FA8650-18-C-7809 ("CIFV"). The views, opinions, and/or findings contained in these articles OR presentations are those of the author(s)/presenter(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.