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00051 #include <linux/kernel.h>
00052 #include <linux/module.h>
00053 #include <linux/moduleparam.h>
00054 #include <linux/init.h>
00055 #include <linux/device.h>
00056 #include <linux/errno.h>
00057 #include <linux/types.h>
00058 #include <linux/stat.h>
00059 #include <linux/version.h>
00060 #include <linux/interrupt.h>
00061
00062 #ifdef LM_INTERFACE
00063 #include <asm/arch/regs-irq.h>
00064 #include <asm/arch/lm.h>
00065 #include <asm/sizes.h>
00066 #endif
00067
00068 # include <linux/irq.h>
00069
00070 #include <asm/io.h>
00071
00072
00073 #include "dwc_os.h"
00074 #include "dwc_otg_dbg.h"
00075 #include "dwc_otg_driver.h"
00076 #include "dwc_otg_attr.h"
00077 #include "dwc_otg_core_if.h"
00078 #include "dwc_otg_pcd_if.h"
00079 #include "dwc_otg_hcd_if.h"
00080
00081 #define DWC_DRIVER_VERSION "2.90a 23-APR-2009"
00082 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
00083
00084 static const char dwc_driver_name[] = "dwc_otg";
00085
00086 extern int pcd_init(
00087 #ifdef LM_INTERFACE
00088 struct lm_device *_dev
00089 #elif PCI_INTERFACE
00090 struct pci_dev *_dev
00091 #endif
00092 );
00093 extern int hcd_init(
00094 #ifdef LM_INTERFACE
00095 struct lm_device *_dev
00096 #elif PCI_INTERFACE
00097 struct pci_dev *_dev
00098 #endif
00099 );
00100
00101 extern int pcd_remove(
00102 #ifdef LM_INTERFACE
00103 struct lm_device *_dev
00104 #elif PCI_INTERFACE
00105 struct pci_dev *_dev
00106 #endif
00107 );
00108
00109 extern void hcd_remove(
00110 #ifdef LM_INTERFACE
00111 struct lm_device *_dev
00112 #elif PCI_INTERFACE
00113 struct pci_dev *_dev
00114 #endif
00115 );
00116
00117
00118
00119
00120 struct dwc_otg_driver_module_params {
00121 int32_t opt;
00122 int32_t otg_cap;
00123 int32_t dma_enable;
00124 int32_t dma_desc_enable;
00125 int32_t dma_burst_size;
00126 int32_t speed;
00127 int32_t host_support_fs_ls_low_power;
00128 int32_t host_ls_low_power_phy_clk;
00129 int32_t enable_dynamic_fifo;
00130 int32_t data_fifo_size;
00131 int32_t dev_rx_fifo_size;
00132 int32_t dev_nperio_tx_fifo_size;
00133 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
00134 int32_t host_rx_fifo_size;
00135 int32_t host_nperio_tx_fifo_size;
00136 int32_t host_perio_tx_fifo_size;
00137 int32_t max_transfer_size;
00138 int32_t max_packet_count;
00139 int32_t host_channels;
00140 int32_t dev_endpoints;
00141 int32_t phy_type;
00142 int32_t phy_utmi_width;
00143 int32_t phy_ulpi_ddr;
00144 int32_t phy_ulpi_ext_vbus;
00145 int32_t i2c_enable;
00146 int32_t ulpi_fs_ls;
00147 int32_t ts_dline;
00148 int32_t en_multiple_tx_fifo;
00149 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
00150 uint32_t thr_ctl;
00151 uint32_t tx_thr_length;
00152 uint32_t rx_thr_length;
00153 int32_t pti_enable;
00154 int32_t mpi_enable;
00155 int32_t lpm_enable;
00156 int32_t ic_usb_cap;
00157 int32_t ahb_thr_ratio;
00158 };
00159
00160 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
00161 .opt = -1,
00162 .otg_cap = -1,
00163 .dma_enable = -1,
00164 .dma_desc_enable = -1,
00165 .dma_burst_size = -1,
00166 .speed = -1,
00167 .host_support_fs_ls_low_power = -1,
00168 .host_ls_low_power_phy_clk = -1,
00169 .enable_dynamic_fifo = -1,
00170 .data_fifo_size = -1,
00171 .dev_rx_fifo_size = -1,
00172 .dev_nperio_tx_fifo_size = -1,
00173 .dev_perio_tx_fifo_size = {
00174
00175 -1,
00176 -1,
00177 -1,
00178 -1,
00179 -1,
00180 -1,
00181 -1,
00182 -1,
00183 -1,
00184 -1,
00185 -1,
00186 -1,
00187 -1,
00188 -1,
00189 -1
00190
00191 },
00192 .host_rx_fifo_size = -1,
00193 .host_nperio_tx_fifo_size = -1,
00194 .host_perio_tx_fifo_size = -1,
00195 .max_transfer_size = -1,
00196 .max_packet_count = -1,
00197 .host_channels = -1,
00198 .dev_endpoints = -1,
00199 .phy_type = -1,
00200 .phy_utmi_width = -1,
00201 .phy_ulpi_ddr = -1,
00202 .phy_ulpi_ext_vbus = -1,
00203 .i2c_enable = -1,
00204 .ulpi_fs_ls = -1,
00205 .ts_dline = -1,
00206 .en_multiple_tx_fifo = -1,
00207 .dev_tx_fifo_size = {
00208
00209 -1,
00210 -1,
00211 -1,
00212 -1,
00213 -1,
00214 -1,
00215 -1,
00216 -1,
00217 -1,
00218 -1,
00219 -1,
00220 -1,
00221 -1,
00222 -1,
00223 -1
00224
00225 },
00226 .thr_ctl = -1,
00227 .tx_thr_length = -1,
00228 .rx_thr_length = -1,
00229 .pti_enable = -1,
00230 .mpi_enable = -1,
00231 .lpm_enable = -1,
00232 .ic_usb_cap = -1,
00233 .ahb_thr_ratio = -1,
00234 };
00235
00239 static ssize_t version_show(struct device_driver *dev, char *buf)
00240 {
00241 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
00242 DWC_DRIVER_VERSION);
00243 }
00244
00245 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
00246
00250 uint32_t g_dbg_lvl = 0;
00251
00255 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
00256 {
00257 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
00258 }
00259
00263 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
00264 size_t count)
00265 {
00266 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
00267 return count;
00268 }
00269
00270 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
00271 dbg_level_store);
00272
00277 static int set_parameters(dwc_otg_core_if_t * core_if)
00278 {
00279 int retval = 0;
00280 int i;
00281
00282 if (dwc_otg_module_params.otg_cap != -1) {
00283 retval +=
00284 dwc_otg_set_param_otg_cap(core_if,
00285 dwc_otg_module_params.otg_cap);
00286 }
00287 if (dwc_otg_module_params.dma_enable != -1) {
00288 retval +=
00289 dwc_otg_set_param_dma_enable(core_if,
00290 dwc_otg_module_params.
00291 dma_enable);
00292 }
00293 if (dwc_otg_module_params.dma_desc_enable != -1) {
00294 retval +=
00295 dwc_otg_set_param_dma_desc_enable(core_if,
00296 dwc_otg_module_params.
00297 dma_desc_enable);
00298 }
00299 if (dwc_otg_module_params.opt != -1) {
00300 retval +=
00301 dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
00302 }
00303 if (dwc_otg_module_params.dma_burst_size != -1) {
00304 retval +=
00305 dwc_otg_set_param_dma_burst_size(core_if,
00306 dwc_otg_module_params.
00307 dma_burst_size);
00308 }
00309 if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
00310 retval +=
00311 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
00312 dwc_otg_module_params.
00313 host_support_fs_ls_low_power);
00314 }
00315 if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
00316 retval +=
00317 dwc_otg_set_param_enable_dynamic_fifo(core_if,
00318 dwc_otg_module_params.
00319 enable_dynamic_fifo);
00320 }
00321 if (dwc_otg_module_params.data_fifo_size != -1) {
00322 retval +=
00323 dwc_otg_set_param_data_fifo_size(core_if,
00324 dwc_otg_module_params.
00325 data_fifo_size);
00326 }
00327 if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
00328 retval +=
00329 dwc_otg_set_param_dev_rx_fifo_size(core_if,
00330 dwc_otg_module_params.
00331 dev_rx_fifo_size);
00332 }
00333 if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
00334 retval +=
00335 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
00336 dwc_otg_module_params.
00337 dev_nperio_tx_fifo_size);
00338 }
00339 if (dwc_otg_module_params.host_rx_fifo_size != -1) {
00340 retval +=
00341 dwc_otg_set_param_host_rx_fifo_size(core_if,
00342 dwc_otg_module_params.host_rx_fifo_size);
00343 }
00344 if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
00345 retval +=
00346 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
00347 dwc_otg_module_params.
00348 host_nperio_tx_fifo_size);
00349 }
00350 if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
00351 retval +=
00352 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
00353 dwc_otg_module_params.
00354 host_perio_tx_fifo_size);
00355 }
00356 if (dwc_otg_module_params.max_transfer_size != -1) {
00357 retval +=
00358 dwc_otg_set_param_max_transfer_size(core_if,
00359 dwc_otg_module_params.
00360 max_transfer_size);
00361 }
00362 if (dwc_otg_module_params.max_packet_count != -1) {
00363 retval +=
00364 dwc_otg_set_param_max_packet_count(core_if,
00365 dwc_otg_module_params.
00366 max_packet_count);
00367 }
00368 if (dwc_otg_module_params.host_channels != -1) {
00369 retval +=
00370 dwc_otg_set_param_host_channels(core_if,
00371 dwc_otg_module_params.
00372 host_channels);
00373 }
00374 if (dwc_otg_module_params.dev_endpoints != -1) {
00375 retval +=
00376 dwc_otg_set_param_dev_endpoints(core_if,
00377 dwc_otg_module_params.
00378 dev_endpoints);
00379 }
00380 if (dwc_otg_module_params.phy_type != -1) {
00381 retval +=
00382 dwc_otg_set_param_phy_type(core_if,
00383 dwc_otg_module_params.phy_type);
00384 }
00385 if (dwc_otg_module_params.speed != -1) {
00386 retval +=
00387 dwc_otg_set_param_speed(core_if,
00388 dwc_otg_module_params.speed);
00389 }
00390 if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
00391 retval +=
00392 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
00393 dwc_otg_module_params.
00394 host_ls_low_power_phy_clk);
00395 }
00396 if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
00397 retval +=
00398 dwc_otg_set_param_phy_ulpi_ddr(core_if,
00399 dwc_otg_module_params.
00400 phy_ulpi_ddr);
00401 }
00402 if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
00403 retval +=
00404 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
00405 dwc_otg_module_params.
00406 phy_ulpi_ext_vbus);
00407 }
00408 if (dwc_otg_module_params.phy_utmi_width != -1) {
00409 retval +=
00410 dwc_otg_set_param_phy_utmi_width(core_if,
00411 dwc_otg_module_params.
00412 phy_utmi_width);
00413 }
00414 if (dwc_otg_module_params.ulpi_fs_ls != -1) {
00415 retval +=
00416 dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_otg_module_params.ulpi_fs_ls);
00417 }
00418 if (dwc_otg_module_params.ts_dline != -1) {
00419 retval +=
00420 dwc_otg_set_param_ts_dline(core_if,
00421 dwc_otg_module_params.ts_dline);
00422 }
00423 if (dwc_otg_module_params.i2c_enable != -1) {
00424 retval +=
00425 dwc_otg_set_param_i2c_enable(core_if,
00426 dwc_otg_module_params.
00427 i2c_enable);
00428 }
00429 if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
00430 retval +=
00431 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
00432 dwc_otg_module_params.
00433 en_multiple_tx_fifo);
00434 }
00435 for (i = 0; i < 15; i++) {
00436 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
00437 retval +=
00438 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
00439 dwc_otg_module_params.
00440 dev_perio_tx_fifo_size
00441 [i], i);
00442 }
00443 }
00444
00445 for (i = 0; i < 15; i++) {
00446 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
00447 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
00448 dwc_otg_module_params.
00449 dev_tx_fifo_size
00450 [i], i);
00451 }
00452 }
00453 if (dwc_otg_module_params.thr_ctl != -1) {
00454 retval +=
00455 dwc_otg_set_param_thr_ctl(core_if,
00456 dwc_otg_module_params.thr_ctl);
00457 }
00458 if (dwc_otg_module_params.mpi_enable != -1) {
00459 retval +=
00460 dwc_otg_set_param_mpi_enable(core_if,
00461 dwc_otg_module_params.
00462 mpi_enable);
00463 }
00464 if (dwc_otg_module_params.pti_enable != -1) {
00465 retval +=
00466 dwc_otg_set_param_pti_enable(core_if,
00467 dwc_otg_module_params.
00468 pti_enable);
00469 }
00470 if (dwc_otg_module_params.lpm_enable != -1) {
00471 retval +=
00472 dwc_otg_set_param_lpm_enable(core_if,
00473 dwc_otg_module_params.
00474 lpm_enable);
00475 }
00476 if (dwc_otg_module_params.ic_usb_cap != -1) {
00477 retval +=
00478 dwc_otg_set_param_ic_usb_cap(core_if,
00479 dwc_otg_module_params.
00480 ic_usb_cap);
00481 }
00482 if (dwc_otg_module_params.tx_thr_length != -1) {
00483 retval +=
00484 dwc_otg_set_param_tx_thr_length(core_if,
00485 dwc_otg_module_params.tx_thr_length);
00486 }
00487 if (dwc_otg_module_params.rx_thr_length != -1) {
00488 retval +=
00489 dwc_otg_set_param_rx_thr_length(core_if,
00490 dwc_otg_module_params.
00491 rx_thr_length);
00492 }
00493 if(dwc_otg_module_params.ahb_thr_ratio != -1) {
00494 retval +=
00495 dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_otg_module_params.ahb_thr_ratio);
00496 }
00497 return retval;
00498 }
00499
00504 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
00505 {
00506 dwc_otg_device_t *otg_dev = dev;
00507 int32_t retval = IRQ_NONE;
00508
00509 retval = dwc_otg_handle_common_intr(otg_dev->core_if);
00510 if (retval != 0) {
00511 S3C2410X_CLEAR_EINTPEND();
00512 }
00513 return IRQ_RETVAL(retval);
00514 }
00515
00525 static void dwc_otg_driver_remove(
00526 #ifdef LM_INTERFACE
00527 struct lm_device *_dev
00528 #elif PCI_INTERFACE
00529 struct pci_dev *_dev
00530 #endif
00531 )
00532
00533 {
00534 #ifdef LM_INTERFACE
00535 dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
00536 #elif PCI_INTERFACE
00537 dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
00538 #endif
00539
00540
00541 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
00542
00543 if (!otg_dev) {
00544
00545 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
00546 return;
00547 }
00548 #ifndef DWC_DEVICE_ONLY
00549 if (otg_dev->hcd) {
00550 hcd_remove(_dev);
00551 } else {
00552 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
00553 return;
00554 }
00555 #endif
00556
00557 #ifndef DWC_HOST_ONLY
00558 if (otg_dev->pcd) {
00559 pcd_remove(_dev);
00560 }
00561 #endif
00562
00563
00564
00565 if (otg_dev->common_irq_installed) {
00566 free_irq(_dev->irq, otg_dev);
00567 }
00568
00569 if (otg_dev->core_if) {
00570 dwc_otg_cil_remove(otg_dev->core_if);
00571 }
00572
00573
00574
00575
00576 dwc_otg_attr_remove(_dev);
00577
00578
00579
00580
00581 if (otg_dev->base) {
00582 iounmap(otg_dev->base);
00583 }
00584 dwc_free(otg_dev);
00585
00586
00587
00588
00589 #ifdef LM_INTERFACE
00590 lm_set_drvdata(_dev, 0);
00591 #elif PCI_INTERFACE
00592 release_mem_region(otg_dev->rsrc_start, otg_dev->rsrc_len);
00593 pci_set_drvdata(_dev, 0);
00594 #endif
00595 }
00596
00608 static int dwc_otg_driver_probe(
00609 #ifdef LM_INTERFACE
00610 struct lm_device *_dev
00611 #elif PCI_INTERFACE
00612 struct pci_dev *_dev, const struct pci_device_id *id
00613 #endif
00614 )
00615 {
00616 int retval = 0;
00617 dwc_otg_device_t *dwc_otg_device;
00618
00619 dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
00620 #ifdef LM_INTERFACE
00621 dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
00622 #elif PCI_INTERFACE
00623 if (!id) {
00624 DWC_ERROR("Invalid pci_device_id %p", id);
00625 return -EINVAL;
00626 }
00627
00628 if (!_dev || (pci_enable_device(_dev) < 0)) {
00629 DWC_ERROR("Invalid pci_device %p", _dev);
00630 return -ENODEV;
00631 }
00632 dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
00633
00634
00635 #endif
00636
00637
00638 dwc_otg_device = dwc_alloc(sizeof(dwc_otg_device_t));
00639
00640 if (!dwc_otg_device) {
00641 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
00642 retval = -ENOMEM;
00643 goto fail;
00644 }
00645
00646 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
00647 dwc_otg_device->reg_offset = 0xFFFFFFFF;
00648
00649
00650
00651
00652 #ifdef LM_INTERFACE
00653 dwc_otg_device->base = ioremap(_dev->resource.start, SZ_256K);
00654
00655 if (!dwc_otg_device->base) {
00656 dev_err(&_dev->dev, "ioremap() failed\n");
00657 retval = -ENOMEM;
00658 goto fail;
00659 }
00660 dev_dbg(&_dev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
00661 #elif PCI_INTERFACE
00662 _dev->current_state = PCI_D0;
00663 _dev->dev.power.power_state = PMSG_ON;
00664
00665 if (!_dev->irq) {
00666 DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", pci_name(_dev));
00667 retval = -ENODEV;
00668 goto fail;
00669 }
00670
00671 dwc_otg_device->rsrc_start = pci_resource_start(_dev,0);
00672 dwc_otg_device->rsrc_len = pci_resource_len(_dev,0);
00673 DWC_DEBUGPL(DBG_ANY,"PCI resource: start=%08x, len=%08x\n",
00674 dwc_otg_device->rsrc_start,
00675 dwc_otg_device->rsrc_len);
00676 if (!request_mem_region(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len, "dwc_otg")) {
00677 dev_dbg(&_dev->dev, "error mapping memory\n");
00678 retval = -EFAULT;
00679 goto fail;
00680 }
00681
00682 dwc_otg_device->base = ioremap_nocache(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len);
00683 if (dwc_otg_device->base == NULL) {
00684 dev_dbg(&_dev->dev, "error mapping memory\n");
00685 retval = -EFAULT;
00686 goto fail;
00687 }
00688 dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", dwc_otg_device->base);
00689 dwc_otg_device->base = (char *)dwc_otg_device->base;
00690 dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", dwc_otg_device->base);
00691 dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
00692 (unsigned)dwc_otg_device->rsrc_start, dwc_otg_device->base);
00693
00694 pci_set_drvdata(_dev, dwc_otg_device);
00695 pci_set_master(_dev);
00696 #endif
00697
00698
00699
00700
00701
00702 #ifdef LM_INTERFACE
00703 lm_set_drvdata(_dev, dwc_otg_device);
00704 #endif
00705 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
00706
00707 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base);
00708 if (!dwc_otg_device->core_if) {
00709 dev_err(&_dev->dev, "CIL initialization failed!\n");
00710 retval = -ENOMEM;
00711 goto fail;
00712 }
00713
00714
00715
00716
00717
00718
00719
00720 if ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
00721 0x4F542000) {
00722 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
00723 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
00724 dwc_otg_cil_remove(dwc_otg_device->core_if);
00725 dwc_free(dwc_otg_device);
00726 retval = -EINVAL;
00727 goto fail;
00728 }
00729
00730
00731
00732
00733 if (set_parameters(dwc_otg_device->core_if)) {
00734 dwc_otg_cil_remove(dwc_otg_device->core_if);
00735 retval = -EINVAL;
00736 goto fail;
00737 }
00738
00739
00740
00741
00742 dwc_otg_attr_create(_dev);
00743
00744
00745
00746
00747
00748 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
00749
00750
00751
00752
00753
00754 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
00755 _dev->irq);
00756 retval = request_irq(_dev->irq, dwc_otg_common_irq,
00757 SA_SHIRQ, "dwc_otg", dwc_otg_device);
00758 if (retval) {
00759 DWC_ERROR("request of irq%d failed\n", _dev->irq);
00760 retval = -EBUSY;
00761 goto fail;
00762 } else {
00763 dwc_otg_device->common_irq_installed = 1;
00764 }
00765
00766 #ifdef LM_INTERFACE
00767 set_irq_type(_dev->irq, IRQT_LOW);
00768 #endif
00769
00770
00771
00772
00773 dwc_otg_core_init(dwc_otg_device->core_if);
00774
00775 #ifndef DWC_HOST_ONLY
00776
00777
00778
00779 retval = pcd_init(_dev);
00780 if (retval != 0) {
00781 DWC_ERROR("pcd_init failed\n");
00782 dwc_otg_device->pcd = NULL;
00783 goto fail;
00784 }
00785 #endif
00786 #ifndef DWC_DEVICE_ONLY
00787
00788
00789
00790 retval = hcd_init(_dev);
00791 if (retval != 0) {
00792 DWC_ERROR("hcd_init failed\n");
00793 dwc_otg_device->hcd = NULL;
00794 goto fail;
00795 }
00796 #endif
00797 #ifdef PCI_INTERFACE
00798 pci_set_drvdata(_dev, dwc_otg_device);
00799 #endif
00800
00801
00802
00803
00804
00805 dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
00806
00807 return 0;
00808
00809 fail:
00810 dwc_otg_driver_remove(_dev);
00811 return retval;
00812 }
00813
00825 #ifdef LM_INTERFACE
00826 static struct lm_driver dwc_otg_driver = {
00827 .drv = {
00828 .name = (char *)dwc_driver_name,
00829 },
00830 .probe = dwc_otg_driver_probe,
00831 .remove = dwc_otg_driver_remove,
00832 };
00833 #elif PCI_INTERFACE
00834 static const struct pci_device_id pci_ids[] = { {
00835 PCI_DEVICE(0x16c3, 0xabcd),
00836 .driver_data = (unsigned long) 0xdeadbeef,
00837 }, { }
00838 };
00839 MODULE_DEVICE_TABLE(pci, pci_ids);
00840
00841
00842 static struct pci_driver dwc_otg_driver = {
00843 .name = "dwc_otg",
00844 .id_table = pci_ids,
00845
00846 .probe = dwc_otg_driver_probe,
00847 .remove = dwc_otg_driver_remove,
00848
00849 .driver = {
00850 .name = (char*)dwc_driver_name,
00851 },
00852 };
00853 #endif
00854
00855
00866 static int __init dwc_otg_driver_init(void)
00867 {
00868 int retval = 0;
00869 int error;
00870 printk(KERN_INFO "%s: version %s\n", dwc_driver_name,
00871 DWC_DRIVER_VERSION);
00872 #ifdef LM_INTERFACE
00873 retval = lm_driver_register(&dwc_otg_driver);
00874 #elif PCI_INTERFACE
00875 retval = pci_register_driver(&dwc_otg_driver);
00876 #endif
00877 if (retval < 0) {
00878 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
00879 return retval;
00880 }
00881 #ifdef LM_INTERFACE
00882 error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version);
00883 error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
00884 #elif PCI_INTERFACE
00885 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
00886 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
00887 #endif
00888 return retval;
00889 }
00890
00891 module_init(dwc_otg_driver_init);
00892
00899 static void __exit dwc_otg_driver_cleanup(void)
00900 {
00901 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
00902
00903 #ifdef LM_INTERFACE
00904 driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
00905 driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
00906 lm_driver_unregister(&dwc_otg_driver);
00907 #elif PCI_INTERFACE
00908 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
00909 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
00910 pci_unregister_driver(&dwc_otg_driver);
00911 #endif
00912
00913 printk(KERN_INFO "%s module removed\n", dwc_driver_name);
00914 }
00915 module_exit(dwc_otg_driver_cleanup);
00916
00917 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
00918 MODULE_AUTHOR("Synopsys Inc.");
00919 MODULE_LICENSE("GPL");
00920
00921 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
00922 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
00923 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
00924 MODULE_PARM_DESC(opt, "OPT Mode");
00925 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
00926 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
00927
00928 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
00929 0444);
00930 MODULE_PARM_DESC(dma_desc_enable,
00931 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
00932
00933 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
00934 0444);
00935 MODULE_PARM_DESC(dma_burst_size,
00936 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
00937 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
00938 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
00939 module_param_named(host_support_fs_ls_low_power,
00940 dwc_otg_module_params.host_support_fs_ls_low_power, int,
00941 0444);
00942 MODULE_PARM_DESC(host_support_fs_ls_low_power,
00943 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
00944 module_param_named(host_ls_low_power_phy_clk,
00945 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
00946 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
00947 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
00948 module_param_named(enable_dynamic_fifo,
00949 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
00950 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
00951 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
00952 0444);
00953 MODULE_PARM_DESC(data_fifo_size,
00954 "Total number of words in the data FIFO memory 32-32768");
00955 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
00956 int, 0444);
00957 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
00958 module_param_named(dev_nperio_tx_fifo_size,
00959 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
00960 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
00961 "Number of words in the non-periodic Tx FIFO 16-32768");
00962 module_param_named(dev_perio_tx_fifo_size_1,
00963 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
00964 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
00965 "Number of words in the periodic Tx FIFO 4-768");
00966 module_param_named(dev_perio_tx_fifo_size_2,
00967 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
00968 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
00969 "Number of words in the periodic Tx FIFO 4-768");
00970 module_param_named(dev_perio_tx_fifo_size_3,
00971 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
00972 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
00973 "Number of words in the periodic Tx FIFO 4-768");
00974 module_param_named(dev_perio_tx_fifo_size_4,
00975 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
00976 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
00977 "Number of words in the periodic Tx FIFO 4-768");
00978 module_param_named(dev_perio_tx_fifo_size_5,
00979 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
00980 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
00981 "Number of words in the periodic Tx FIFO 4-768");
00982 module_param_named(dev_perio_tx_fifo_size_6,
00983 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
00984 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
00985 "Number of words in the periodic Tx FIFO 4-768");
00986 module_param_named(dev_perio_tx_fifo_size_7,
00987 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
00988 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
00989 "Number of words in the periodic Tx FIFO 4-768");
00990 module_param_named(dev_perio_tx_fifo_size_8,
00991 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
00992 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
00993 "Number of words in the periodic Tx FIFO 4-768");
00994 module_param_named(dev_perio_tx_fifo_size_9,
00995 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
00996 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
00997 "Number of words in the periodic Tx FIFO 4-768");
00998 module_param_named(dev_perio_tx_fifo_size_10,
00999 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
01000 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
01001 "Number of words in the periodic Tx FIFO 4-768");
01002 module_param_named(dev_perio_tx_fifo_size_11,
01003 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
01004 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
01005 "Number of words in the periodic Tx FIFO 4-768");
01006 module_param_named(dev_perio_tx_fifo_size_12,
01007 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
01008 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
01009 "Number of words in the periodic Tx FIFO 4-768");
01010 module_param_named(dev_perio_tx_fifo_size_13,
01011 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
01012 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
01013 "Number of words in the periodic Tx FIFO 4-768");
01014 module_param_named(dev_perio_tx_fifo_size_14,
01015 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
01016 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
01017 "Number of words in the periodic Tx FIFO 4-768");
01018 module_param_named(dev_perio_tx_fifo_size_15,
01019 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
01020 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
01021 "Number of words in the periodic Tx FIFO 4-768");
01022 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
01023 int, 0444);
01024 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
01025 module_param_named(host_nperio_tx_fifo_size,
01026 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
01027 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
01028 "Number of words in the non-periodic Tx FIFO 16-32768");
01029 module_param_named(host_perio_tx_fifo_size,
01030 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
01031 MODULE_PARM_DESC(host_perio_tx_fifo_size,
01032 "Number of words in the host periodic Tx FIFO 16-32768");
01033 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
01034 int, 0444);
01036 MODULE_PARM_DESC(max_transfer_size,
01037 "The maximum transfer size supported in bytes 2047-65535");
01038 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
01039 int, 0444);
01040 MODULE_PARM_DESC(max_packet_count,
01041 "The maximum number of packets in a transfer 15-511");
01042 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
01043 0444);
01044 MODULE_PARM_DESC(host_channels,
01045 "The number of host channel registers to use 1-16");
01046 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
01047 0444);
01048 MODULE_PARM_DESC(dev_endpoints,
01049 "The number of endpoints in addition to EP0 available for device mode 1-15");
01050 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
01051 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
01052 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
01053 0444);
01054 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
01055 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
01056 MODULE_PARM_DESC(phy_ulpi_ddr,
01057 "ULPI at double or single data rate 0=Single 1=Double");
01058 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
01059 int, 0444);
01060 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
01061 "ULPI PHY using internal or external vbus 0=Internal");
01062 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
01063 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
01064 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
01065 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
01066 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
01067 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
01068 module_param_named(debug, g_dbg_lvl, int, 0444);
01069 MODULE_PARM_DESC(debug, "");
01070
01071 module_param_named(en_multiple_tx_fifo,
01072 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
01073 MODULE_PARM_DESC(en_multiple_tx_fifo,
01074 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
01075 module_param_named(dev_tx_fifo_size_1,
01076 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
01077 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
01078 module_param_named(dev_tx_fifo_size_2,
01079 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
01080 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
01081 module_param_named(dev_tx_fifo_size_3,
01082 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
01083 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
01084 module_param_named(dev_tx_fifo_size_4,
01085 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
01086 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
01087 module_param_named(dev_tx_fifo_size_5,
01088 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
01089 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
01090 module_param_named(dev_tx_fifo_size_6,
01091 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
01092 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
01093 module_param_named(dev_tx_fifo_size_7,
01094 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
01095 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
01096 module_param_named(dev_tx_fifo_size_8,
01097 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
01098 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
01099 module_param_named(dev_tx_fifo_size_9,
01100 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
01101 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
01102 module_param_named(dev_tx_fifo_size_10,
01103 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
01104 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
01105 module_param_named(dev_tx_fifo_size_11,
01106 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
01107 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
01108 module_param_named(dev_tx_fifo_size_12,
01109 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
01110 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
01111 module_param_named(dev_tx_fifo_size_13,
01112 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
01113 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
01114 module_param_named(dev_tx_fifo_size_14,
01115 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
01116 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
01117 module_param_named(dev_tx_fifo_size_15,
01118 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
01119 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
01120
01121 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
01122 MODULE_PARM_DESC(thr_ctl,
01123 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
01124 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
01125 0444);
01126 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
01127 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
01128 0444);
01129 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
01130
01131 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
01132 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
01133 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
01134 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
01135 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
01136 MODULE_PARM_DESC(ic_usb_cap,
01137 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
01138 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444);
01139 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
01140
