Supervisions for VLSI Design will be organsised by the Computer Laboratory.

The following questions are suggested for three supervisions, but individual supervisors might set different work.

Exercises for the first supervision

• CST 1995 Paper 7 Question 2 (CMOS NAND designs)
  Draw both the stick diagram and the layout. The discussion about symmetric rise and fall times requires some thought about the relative resistances of conducting n-channel and p-channel FETs.
• CST 1999 Paper 7 Question 1 (PLAs)
  Note that the primes after signal names indicate inversion, so there are three primary inputs and their inverses to be considered.
• CST 2001 Paper 9 Question 2 (Dynamic latch)
• CST 2000 Paper 9 Question 2 (Memory designs)
• CST 1986 Paper 1 Question 1 (Circuit analysis)

Exercises for the second supervision

• CST 1995 Paper 9 Question 1 (Design styles)
• CST 1997 Paper 9 Question 4 (Clocking)
• CST 2002 Paper 9 Question 2 (Carry propagation)
• CST 2003 Paper 9 Question 2 (Carry propagation)
• CST 2001 Paper 8 Question 2 (Scaling)

Exercises for the third supervision

• CST 1998 Paper 7 Question 1 (CMOS invertors)
• CST 2003 Paper 8 Question 2 (XOR designs)
• CST 2002 Paper 8 Question 2 (NAND gates)
• CST 2000 Paper 7 Question 2 (Circuit analysis)
• CST 1999 Paper 9 Question 2 (Muller C element)