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Alternatives to RTL

Higher-level entry forms are ideally needed, perhaps schedulling within a thread at compile-time and between threads at run time ?

High-level Synthesis (HLS) essentially converts software to hardware. Classically it take one thread and a fixed body of code and it

unwinds inner loops by some factor,
generates a custom datapath containing registers, RAMs and ALUs
and a custom sequencer that implements an efficient, static schedule

that achieves the same behaviour as the original program.

It will generally deploy state re-encoding and re-pipelining to meet timing closure and power budgets. Greaves wrote an HLS program in around 1990 that was commercially licensed: »CTOV Bubble SorterExample. These ideas are only now being seriously considered by industry, with all major tools providers now offering a C-to-gates compiler. »LegUp from Toronto is a modern equivalent.

The »Kiwi Compiler uses similar approaches for acceleration of big data algorithms expressed in concurrent CSharp on FPGA.

For the future, the following two look promising: »Chisel: Constructing Hardware in a Scala-Embedded Language and »HardCaml - Register Transfer Level Hardware Design in OCaml