Bubble Sorter Example

Here is a very simple example of CTOV capabilities. This example uses an array to perform bubble sort. By default, CTOV turns small array's into flip-flops and larger arrays into RAMs. RAMs can be internal or external to the design. Infact CTOV has extensive array packing features, supporting anything from all variables being in one RAM to all variables being in flip-flops with various multiple multi-ported RAM options being the norm.

In this example, we generate some numbers and then place them in an array. The array is scalarised into flip-flops in the first compilation and held as a RAM in the second compilation. The array is then sorted using bubble sort.


The compiler was invoked with the command line

    ctov -oroot xmas -iroot xmas -read tests/xmas.cpp  \
             --  -keepintermediates -o tests/xmas.v 

Here is the C++ source code

//
#include "systemc.h"
#include "cxcpptypes.h"

SC_MODULE(xmas)
{
  sc_in <bool> clk, reset;
  sc_in <bool> a;
  sc_out <sc_uint<10> > present;
  sc_out <bool> done;

  void xmas::toggler();

  u1 yin, yan;
  bool b;

  SC_CTOR(xmas)
    {
      SC_METHOD(toggler);
      sensitive_pos < clk;
    };

};


#define NELEMENTS 12
 
u8 xp[NELEMENTS];

void xmas::toggler()
{
  int i, j;
  done = 0;
  // Generate some data:
  for (i=0;i<NELEMENTS;i+=1)
    {
      xp[i] = (9*i) % 31;
      tt_display("Data generated i=%d %d", i, xp[i]);
      cx_barrier();   
    }

  // Bubble sort the data
  for (j=0;j<NELEMENTS;j+=1)
    for (i=0;i<NELEMENTS-1;i+=1)
      {
	if (xp[i] > xp[i+1]) 
	  { u32 t = xp[i]; xp[i] = xp[i+1]; xp[i+1] = t; }
	cx_barrier();   
      }


  // Print it out
  for (i=0;i<NELEMENTS;i+=1)
    {
      tt_display("Sorted i=%d %d", i, xp[i]);
      cx_barrier();   
    }


  tt_display("Final value of loc 2 was %h\n", xp[2]);
  present = xp[1];
  cx_barrier();
  done = 1;
  cx_barrier();
}

// end of file



Here is a test wrapper for running the generated Verilog:

module SIMSYS();
  reg clk, reset;
  wire [9:0] xmas_present;
  wire a, done;

  xmas thexmas(.done(done), .present(xmas_present), .reset(reset), .clk(clk), .a(a));

  assign a = 1;

  always @(posedge clk) if (done) begin
	$display("Done signal asserted at time %t", $time);
	#30 $finish;
	end

  initial begin
	#5 clk = 0; reset = 1;
 	#5 clk = 1; 
 	#5 clk = 0;
 	#5 clk = 1; 
        reset = 0;
 	#5 forever begin
	 	#5 clk = 1; 
	 	#5 clk = 0;
		end
	end

endmodule



And here is the simulator output for the first compilation:

$ csnox tests/xmas.v -clearnet  tests/xmassys.v
Hard reset
Compiled to 678 words pcode, giving 125 ready threads.
Simulating....
Data generated i=00 00
Data generated i=00 00
Data generated i=01 09
Data generated i=02 18
Data generated i=03 27
Data generated i=04 05
Data generated i=05 14
Data generated i=06 23
Data generated i=07 01
Data generated i=08 10
Data generated i=09 19
Data generated i=10 28
Data generated i=11 06
Sorted i=00 0
Sorted i=01 1
Sorted i=02 5
Sorted i=03 6
Sorted i=04 9
Sorted i=05 10
Sorted i=06 14
Sorted i=07 18
Sorted i=08 19
Sorted i=09 23
Sorted i=10 27
Sorted i=11 28
Final value of loc 2 was 0x5

Done signal asserted at time          1740
CSIM Simulator Finishing

This example mixes bits of Tenos and bits of SystemC in its input format. The compiler currently supports such a mix although we would not expect users to deliberately create such mixes.

A notable feature are the calls to `cx_barrier()'. These have been inserted inside the body of each loop, forcing the loops to be preserved and executed one lap per clock tick in the final model. Executing a barrier causes all symbolically evaluated expressions to be committed to hardware resources (registers or RAM locations). If the barriers are left out, then the whole loop is unwound at compile time. However, this is only possible when sorting small arrays that are scalarised to flip-flops. Larger arrays, when mapped to, say, a single ported RAM, will require multiple clock-ticks as the accesses are sequenced.

A main feature of CTOV is that it will insert barriers when it needs to but otherwise will attempt to do as much as possible in parallel. Serialisation is forced when the user maps data to resources, including RAMs and ALUs. These only support limited data throughput, and hence are scheduled for different operations on a cycle-by-cycle basis by the tool. Sometimes it is impossible to tell at compile time whether two subscripts refer to the same array location (halting problem) and so in these undecidable cases, the tool inserts an automatic barrier statement to flush out all data state to the hardware resources. It can then continue with a clean slate.

Here is the Verilog generated by CTOV in this compilation:

 ctov -oroot xmas -iroot xmas -read tests/xmas.cpp -- -keepintermediates -o tests/xmas.v  */
/* User=djg  */
/* WE ACCEPT NO LIABILITY FOR CONSEQUENTIAL LOSS FROM USING THESE EARLY VERSIONS OF OUR PRODUCTS */

/* Output from TT C++/CTOV Version=C++ Alpha 0.0 5-Jan-02 tan */

/* CXCCFE call /home/djg/d300/ctov/cxccfe/cxccfe -o tests/xmas.pt -DSYNTHESIS -DTTCTOV  -nostdinc  -I-  -I/home/djg/d300/ctov/cxinclude -I.:/home/djg/verilog/techlibs:/home/djg/verilog/djg-verilog-library  -Itests/ tests/xmas.cpp */


module xmas (clk, reset, done, present);
  supply0 LGND; supply1 LVCC;
  input clk;
  input reset;
  output done;
  reg done;
  output [9:0] present;
  reg [9:0] present;
  wire cxpin_1242;
  wire cxpin_1241;
  wire cxpin_1240;
  wire cxpin_1239;
  wire cxpin_1238;
  wire cxpin_1237;
  wire cxpin_1236;
  wire cxpin_1235;
  wire cxpin_1135;
  wire cxpin_1134;
  wire cxpin_1131;
  wire cxpin_1130;
  wire cxpin_1122;
  wire cxpin_1121;
  wire cxpin_1120;
  wire cxpin_1119;
  wire cxpin_1118;
  wire cxpin_1117;
  wire cxpin_1111;
  wire cxpin_1110;
  wire cxpin_1109;
  wire cxpin_1108;
  wire cxpin_1107;
  wire cxpin_1104;
  wire cxpin_1103;
  wire [31:0] LOGICPIN_1079;
  wire [7:0] LOGICPIN_1033;
  wire [7:0] LOGICPIN_1179;
  wire [7:0] LOGICPIN_1023;
  wire [31:0] LOGICPIN_1082;
  wire LOGICPIN_1045;
  wire [7:0] LOGICPIN_1203;
  wire LOGICPIN_1069;
  wire LOGICPIN_1060;
  wire [7:0] LOGICPIN_1019;
  wire [7:0] LOGICPIN_1038;
  wire [31:0] LOGICPIN_1085;
  wire LOGICPIN_1073;
  wire [7:0] LOGICPIN_1028;
  wire [7:0] LOGICPIN_1219;
  wire [7:0] LOGICPIN_1136;
  wire [7:0] LOGICPIN_1030;
  wire [31:0] LOGICPIN_1087;
  wire [7:0] LOGICPIN_1034;
  wire [7:0] LOGICPIN_1137;
  wire [31:0] LOGICPIN_1077;
  wire [7:0] LOGICPIN_1147;
  wire [7:0] LOGICPIN_1024;
  wire [31:0] LOGICPIN_1075;
  wire [7:0] LOGICPIN_1163;
  wire [7:0] LOGICPIN_1156;
  wire [7:0] LOGICPIN_1164;
  wire [31:0] LOGICPIN_1080;
  wire [7:0] LOGICPIN_1172;
  wire [7:0] LOGICPIN_1020;
  wire LOGICPIN_1041;
  wire [7:0] LOGICPIN_1039;
  wire [7:0] LOGICPIN_1180;
  wire LOGICPIN_1007;
  wire [7:0] LOGICPIN_1187;
  wire [7:0] LOGICPIN_1188;
  wire [31:0] LOGICPIN_1083;
  wire [7:0] LOGICPIN_1196;
  wire [7:0] LOGICPIN_1035;
  wire [7:0] LOGICPIN_1204;
  wire [7:0] LOGICPIN_1211;
  wire [7:0] LOGICPIN_1212;
  wire [7:0] LOGICPIN_1025;
  wire LOGICPIN_1062;
  wire [7:0] LOGICPIN_1220;
  wire [31:0] LOGICPIN_1086;
  wire LOGICPIN_1072;
  wire LOGICPIN_1052;
  wire [7:0] LOGICPIN_1031;
  wire [7:0] LOGICPIN_1228;
  wire LOGICPIN_1100;
  wire [7:0] LOGICPIN_1146;
  wire [7:0] LOGICPIN_1021;
  wire [7:0] LOGICPIN_1040;
  wire LOGICPIN_1043;
  wire [31:0] LOGICPIN_1078;
  wire [31:0] LOGICPIN_1001;
  wire [7:0] LOGICPIN_1227;
  wire [7:0] LOGICPIN_1171;
  wire [7:0] LOGICPIN_1036;
  wire [31:0] LOGICPIN_1088;
  wire LOGICPIN_1283;
  wire [31:0] LOGICPIN_1081;
  wire [7:0] LOGICPIN_1026;
  wire LOGICPIN_1270;
  wire [31:0] LOGICPIN_1029;
  wire LOGICPIN_1068;
  wire [7:0] LOGICPIN_1195;
  wire LOGICPIN_1067;
  wire [7:0] LOGICPIN_1032;
  wire LOGICPIN_1005;
  wire [31:0] LOGICPIN_1084;
  wire LOGICPIN_1070;
  wire [7:0] LOGICPIN_1022;
  wire [7:0] LOGICPIN_1018;
  wire LOGICPIN_1047;
  wire LOGICPIN_1101;
  wire LOGICPIN_1071;
  wire [7:0] LOGICPIN_1037;
  wire [31:0] LOGICPIN_1076;
  wire [7:0] LOGICPIN_1155;
  wire [7:0] LOGICPIN_1027;
  reg [7:0] xp__11;
  reg [7:0] xp__10;
  reg [7:0] xp__9;
  reg [7:0] xp__8;
  reg [7:0] xp__7;
  reg [7:0] xp__6;
  reg [7:0] xp__5;
  reg [7:0] xp__4;
  reg [7:0] xp__3;
  reg [7:0] xp__0;
  reg [7:0] xp__2;
  reg [7:0] xp__1;
  reg [31:0] j;
  reg [31:0] t;
  reg [31:0] i;
  wire ac_alpha_zero;
  wire ac_ttf101toptLLLL3Lbar;
  wire ac_ttf101topTLLLL3Lbar;
  wire ac_ttf102topbar;
  wire ac_ttf103toptLLtLLL3Lbar;
  wire ac_ttf103toptLLLL1Lbar;
  wire ac_ttf103topTLLtLLL3Lbar;
  wire ac_ttf103topTLLLL1Lbar;
  wire ac_ttf104toptLLLL1Lbar;
  wire ac_ttf104topTLLLL1Lbar;
  wire ac_ttf104brkLLLL2Lbar;
  wire ac_ttf104brkLLLL6Lbar;
  reg [4:0] tt_statereg;


 always @(posedge clk) begin tt_statereg <= (reset) ?
 0:((LOGICPIN_1001-12>>31^(LOGICPIN_1001>>31 &&
 !(LOGICPIN_1001-12>>31)) && ac_ttf101toptLLLL3Lbar) ||
 (LOGICPIN_1001-12>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-12>>31))
 && ac_ttf101topTLLLL3Lbar)) ? 1:(ac_alpha_zero) ? 2:((LOGICPIN_1005
 && ac_ttf101toptLLLL3Lbar) || ((LOGICPIN_1007 &&
 ac_ttf103toptLLLL1Lbar) || ((LOGICPIN_1007 && ac_ttf103topTLLLL1Lbar)
 || ((LOGICPIN_1007 && ac_ttf103topTLLtLLL3Lbar) || ((LOGICPIN_1007 &&
 ac_ttf103toptLLtLLL3Lbar) || (LOGICPIN_1005 &&
 ac_ttf101topTLLLL3Lbar)))))) ?
 3:((LOGICPIN_1040-LOGICPIN_1028>>7^(((!(LOGICPIN_1040>>7) &&
 LOGICPIN_1028>>7) && LOGICPIN_1040-LOGICPIN_1028>>7) ||
 ((LOGICPIN_1040>>7 && !(LOGICPIN_1028>>7)) &&
 !(LOGICPIN_1040-LOGICPIN_1028>>7))) && LOGICPIN_1041) ||
 ((LOGICPIN_1040-LOGICPIN_1028>>7^(((!(LOGICPIN_1040>>7) &&
 LOGICPIN_1028>>7) && LOGICPIN_1040-LOGICPIN_1028>>7) ||
 ((LOGICPIN_1040>>7 && !(LOGICPIN_1028>>7)) &&
 !(LOGICPIN_1040-LOGICPIN_1028>>7))) && LOGICPIN_1043) ||
 ((LOGICPIN_1040-LOGICPIN_1028>>7^(((!(LOGICPIN_1040>>7) &&
 LOGICPIN_1028>>7) && LOGICPIN_1040-LOGICPIN_1028>>7) ||
 ((LOGICPIN_1040>>7 && !(LOGICPIN_1028>>7)) &&
 !(LOGICPIN_1040-LOGICPIN_1028>>7))) && LOGICPIN_1045) ||
 (LOGICPIN_1040-LOGICPIN_1028>>7^(((!(LOGICPIN_1040>>7) &&
 LOGICPIN_1028>>7) && LOGICPIN_1040-LOGICPIN_1028>>7) ||
 ((LOGICPIN_1040>>7 && !(LOGICPIN_1028>>7)) &&
 !(LOGICPIN_1040-LOGICPIN_1028>>7))) && LOGICPIN_1047)))) ?
 4:((LOGICPIN_1052 && LOGICPIN_1041) || ((LOGICPIN_1052 &&
 LOGICPIN_1043) || ((LOGICPIN_1052 && LOGICPIN_1045) || (LOGICPIN_1052
 && LOGICPIN_1047)))) ? 5:(xp__1-xp__0>>7^(((!(xp__1>>7) && xp__0>>7)
 && xp__1-xp__0>>7) || ((xp__1>>7 && !(xp__0>>7)) &&
 !(xp__1-xp__0>>7))) && LOGICPIN_1060) ? 6:(LOGICPIN_1062 &&
 LOGICPIN_1060) ? 7:((LOGICPIN_1001-12>>31^(LOGICPIN_1001>>31 &&
 !(LOGICPIN_1001-12>>31)) && ac_ttf104toptLLLL1Lbar) ||
 (LOGICPIN_1001-12>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-12>>31))
 && ac_ttf104topTLLLL1Lbar)) ? 8:(LOGICPIN_1068) ? 9:(LOGICPIN_1071) ?
 10:(ac_ttf104brkLLLL2Lbar) ? 11:tt_statereg;

  present <= (cxpin_1104 || cxpin_1103) ? xp__1:present;

  t <= (cxpin_1111) ? xp__0:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1028:t;

  j <= (cxpin_1122 || cxpin_1121) ? 0:(cxpin_1120 || (cxpin_1119 || (cxpin_1118 || cxpin_1117))) ? 1+j:j;

  done <= (cxpin_1131) ? 0:(cxpin_1130) ? 1:done;

  xp__0 <= (cxpin_1131) ? 0:(cxpin_1135 || cxpin_1134) ? LOGICPIN_1077:(cxpin_1111) ? xp__1:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1137:xp__0;

  xp__1 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1078:(cxpin_1111) ? xp__0:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1147:xp__1;

  xp__2 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1079:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1156:xp__2;

  xp__3 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1080:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1164:xp__3;

  xp__4 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1081:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1172:xp__4;

  xp__5 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1082:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1180:xp__5;

  xp__6 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1083:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1188:xp__6;

  xp__7 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1084:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1196:xp__7;

  xp__8 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1085:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1204:xp__8;

  xp__9 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1086:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1212:xp__9;

  xp__10 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1087:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1220:xp__10;

  xp__11 <= (cxpin_1135 || cxpin_1134) ? LOGICPIN_1088:(cxpin_1110 || (cxpin_1109 || (cxpin_1108 || cxpin_1107))) ? LOGICPIN_1228:xp__11;

  i <= (cxpin_1131) ? 0:(cxpin_1122 || (cxpin_1135 || (cxpin_1121 || cxpin_1134))) ? LOGICPIN_1001:(cxpin_1242 || (cxpin_1241 || cxpin_1111)) ? 0:(cxpin_1240 || (cxpin_1110 || (cxpin_1120 || (cxpin_1239 || (cxpin_1109 || (cxpin_1119 || (cxpin_1238 || (cxpin_1108 || (cxpin_1118 || (cxpin_1237 || (cxpin_1107 || (cxpin_1117 || (cxpin_1104 || (cxpin_1236 || (cxpin_1103 || cxpin_1235))))))))))))))) ? LOGICPIN_1001:i;

 if (ac_alpha_zero) $display("Data generated i=%d %d", 0, 0);

 if (LOGICPIN_1072 || LOGICPIN_1073) $display("Data generated i=%d %d", LOGICPIN_1001, (0==LOGICPIN_1001) ? LOGICPIN_1077:(1==LOGICPIN_1001) ? LOGICPIN_1078:(2==LOGICPIN_1001) ? LOGICPIN_1079:(3==LOGICPIN_1001) ? LOGICPIN_1080:(4==LOGICPIN_1001) ? LOGICPIN_1081:(5==LOGICPIN_1001) ? LOGICPIN_1082:(6==LOGICPIN_1001) ? LOGICPIN_1083:(7==LOGICPIN_1001) ? LOGICPIN_1084:(8==LOGICPIN_1001) ? LOGICPIN_1085:(9==LOGICPIN_1001) ? LOGICPIN_1086:(10==LOGICPIN_1001) ? LOGICPIN_1087:LOGICPIN_1088);

 if (LOGICPIN_1068) $display("Sorted i=%d %d", 0, xp__0);

 if (LOGICPIN_1100 || LOGICPIN_1101) $display("Sorted i=%d %d", LOGICPIN_1001, LOGICPIN_1028);

 if (LOGICPIN_1071) $display("Final value of loc 2 was %h
", xp__2);

  end
  assign LOGICPIN_1079  = (LOGICPIN_1001==2) ? LOGICPIN_1076:xp__2;
  assign LOGICPIN_1033  = (7==LOGICPIN_1029) ? xp__7:LOGICPIN_1032;
  assign LOGICPIN_1179  = (LOGICPIN_1001==5) ? LOGICPIN_1040:xp__5;
  assign LOGICPIN_1023  = (5==LOGICPIN_1001) ? xp__5:LOGICPIN_1022;
  assign LOGICPIN_1082  = (LOGICPIN_1001==5) ? LOGICPIN_1076:xp__5;
  assign LOGICPIN_1045  = LOGICPIN_1001-11>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-11>>31)) && ac_ttf103toptLLLL1Lbar;
  assign LOGICPIN_1203  = (LOGICPIN_1001==8) ? LOGICPIN_1040:xp__8;
  assign LOGICPIN_1069  = LOGICPIN_1005 && ac_ttf104topTLLLL1Lbar;
  assign LOGICPIN_1060  = j-12>>31^(j>>31 && !(j-12>>31)) && ac_ttf102topbar;
  assign LOGICPIN_1019  = (9==LOGICPIN_1001) ? xp__9:LOGICPIN_1018;
  assign LOGICPIN_1038  = (2==LOGICPIN_1029) ? xp__2:LOGICPIN_1037;
  assign LOGICPIN_1085  = (LOGICPIN_1001==8) ? LOGICPIN_1076:xp__8;
  assign LOGICPIN_1073  = ac_ttf101toptLLLL3Lbar && LOGICPIN_1001-12>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-12>>31));
  assign LOGICPIN_1028  = (0==LOGICPIN_1001) ? xp__0:LOGICPIN_1027;
  assign LOGICPIN_1219  = (LOGICPIN_1001==10) ? LOGICPIN_1040:xp__10;
  assign LOGICPIN_1136  = (LOGICPIN_1001==0) ? LOGICPIN_1040:xp__0;
  assign LOGICPIN_1030  = (10==LOGICPIN_1029) ? xp__10:xp__11;
  assign LOGICPIN_1087  = (LOGICPIN_1001==10) ? LOGICPIN_1076:xp__10;
  assign LOGICPIN_1034  = (6==LOGICPIN_1029) ? xp__6:LOGICPIN_1033;
  assign LOGICPIN_1137  = (LOGICPIN_1029==0) ? LOGICPIN_1028:LOGICPIN_1136;
  assign LOGICPIN_1077  = (LOGICPIN_1001==0) ? LOGICPIN_1076:xp__0;
  assign LOGICPIN_1147  = (LOGICPIN_1029==1) ? LOGICPIN_1028:LOGICPIN_1146;
  assign LOGICPIN_1024  = (4==LOGICPIN_1001) ? xp__4:LOGICPIN_1023;
  assign LOGICPIN_1075  = 9*LOGICPIN_1001;
  assign LOGICPIN_1163  = (LOGICPIN_1001==3) ? LOGICPIN_1040:xp__3;
  assign LOGICPIN_1156  = (LOGICPIN_1029==2) ? LOGICPIN_1028:LOGICPIN_1155;
  assign LOGICPIN_1164  = (LOGICPIN_1029==3) ? LOGICPIN_1028:LOGICPIN_1163;
  assign LOGICPIN_1080  = (LOGICPIN_1001==3) ? LOGICPIN_1076:xp__3;
  assign LOGICPIN_1172  = (LOGICPIN_1029==4) ? LOGICPIN_1028:LOGICPIN_1171;
  assign LOGICPIN_1020  = (8==LOGICPIN_1001) ? xp__8:LOGICPIN_1019;
  assign LOGICPIN_1041  = LOGICPIN_1001-11>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-11>>31)) && ac_ttf103topTLLtLLL3Lbar;
  assign LOGICPIN_1039  = (1==LOGICPIN_1029) ? xp__1:LOGICPIN_1038;
  assign LOGICPIN_1180  = (LOGICPIN_1029==5) ? LOGICPIN_1028:LOGICPIN_1179;
  assign LOGICPIN_1007  = !(LOGICPIN_1001-11>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-11>>31)));
  assign LOGICPIN_1187  = (LOGICPIN_1001==6) ? LOGICPIN_1040:xp__6;
  assign LOGICPIN_1188  = (LOGICPIN_1029==6) ? LOGICPIN_1028:LOGICPIN_1187;
  assign LOGICPIN_1083  = (LOGICPIN_1001==6) ? LOGICPIN_1076:xp__6;
  assign LOGICPIN_1196  = (LOGICPIN_1029==7) ? LOGICPIN_1028:LOGICPIN_1195;
  assign LOGICPIN_1035  = (5==LOGICPIN_1029) ? xp__5:LOGICPIN_1034;
  assign LOGICPIN_1204  = (LOGICPIN_1029==8) ? LOGICPIN_1028:LOGICPIN_1203;
  assign LOGICPIN_1211  = (LOGICPIN_1001==9) ? LOGICPIN_1040:xp__9;
  assign LOGICPIN_1212  = (LOGICPIN_1029==9) ? LOGICPIN_1028:LOGICPIN_1211;
  assign LOGICPIN_1025  = (3==LOGICPIN_1001) ? xp__3:LOGICPIN_1024;
  assign LOGICPIN_1062  = !(xp__1-xp__0>>7^(((!(xp__1>>7) && xp__0>>7) && xp__1-xp__0>>7) || ((xp__1>>7 && !(xp__0>>7)) && !(xp__1-xp__0>>7))));
  assign LOGICPIN_1220  = (LOGICPIN_1029==10) ? LOGICPIN_1028:LOGICPIN_1219;
  assign LOGICPIN_1086  = (LOGICPIN_1001==9) ? LOGICPIN_1076:xp__9;
  assign LOGICPIN_1072  = ac_ttf101topTLLLL3Lbar && LOGICPIN_1001-12>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-12>>31));
  assign LOGICPIN_1052  = !(LOGICPIN_1040-LOGICPIN_1028>>7^(((!(LOGICPIN_1040>>7) && LOGICPIN_1028>>7) && LOGICPIN_1040-LOGICPIN_1028>>7) || ((LOGICPIN_1040>>7 && !(LOGICPIN_1028>>7)) && !(LOGICPIN_1040-LOGICPIN_1028>>7))));
  assign LOGICPIN_1031  = (9==LOGICPIN_1029) ? xp__9:LOGICPIN_1030;
  assign LOGICPIN_1228  = (LOGICPIN_1029==11) ? LOGICPIN_1028:LOGICPIN_1227;
  assign LOGICPIN_1100  = ac_ttf104topTLLLL1Lbar && LOGICPIN_1001-12>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-12>>31));
  assign LOGICPIN_1146  = (LOGICPIN_1001==1) ? LOGICPIN_1040:xp__1;
  assign LOGICPIN_1021  = (7==LOGICPIN_1001) ? xp__7:LOGICPIN_1020;
  assign LOGICPIN_1040  = (0==LOGICPIN_1029) ? xp__0:LOGICPIN_1039;
  assign LOGICPIN_1043  = LOGICPIN_1001-11>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-11>>31)) && ac_ttf103toptLLtLLL3Lbar;
  assign LOGICPIN_1078  = (LOGICPIN_1001==1) ? LOGICPIN_1076:xp__1;
  assign LOGICPIN_1001  = 1+i;
  assign LOGICPIN_1227  = (LOGICPIN_1001==11) ? LOGICPIN_1040:xp__11;
  assign LOGICPIN_1171  = (LOGICPIN_1001==4) ? LOGICPIN_1040:xp__4;
  assign LOGICPIN_1036  = (4==LOGICPIN_1029) ? xp__4:LOGICPIN_1035;
  assign LOGICPIN_1088  = (LOGICPIN_1001==11) ? LOGICPIN_1076:xp__11;
  assign LOGICPIN_1283  = LOGICPIN_1001-11>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-11>>31)) && LOGICPIN_1040-LOGICPIN_1028>>7^(((!(LOGICPIN_1040>>7) && LOGICPIN_1028>>7) && LOGICPIN_1040-LOGICPIN_1028>>7) || ((LOGICPIN_1040>>7 && !(LOGICPIN_1028>>7)) && !(LOGICPIN_1040-LOGICPIN_1028>>7)));
  assign LOGICPIN_1081  = (LOGICPIN_1001==4) ? LOGICPIN_1076:xp__4;
  assign LOGICPIN_1026  = (2==LOGICPIN_1001) ? xp__2:LOGICPIN_1025;
  assign LOGICPIN_1270  = LOGICPIN_1001-11>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-11>>31)) && LOGICPIN_1052;
  assign LOGICPIN_1029  = 1+LOGICPIN_1001;
  assign LOGICPIN_1068  = LOGICPIN_1067 && ac_ttf102topbar;
  assign LOGICPIN_1195  = (LOGICPIN_1001==7) ? LOGICPIN_1040:xp__7;
  assign LOGICPIN_1067  = !(j-12>>31^(j>>31 && !(j-12>>31)));
  assign LOGICPIN_1032  = (8==LOGICPIN_1029) ? xp__8:LOGICPIN_1031;
  assign LOGICPIN_1005  = !(LOGICPIN_1001-12>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-12>>31)));
  assign LOGICPIN_1084  = (LOGICPIN_1001==7) ? LOGICPIN_1076:xp__7;
  assign LOGICPIN_1070  = LOGICPIN_1005 && ac_ttf104toptLLLL1Lbar;
  assign LOGICPIN_1022  = (6==LOGICPIN_1001) ? xp__6:LOGICPIN_1021;
  assign LOGICPIN_1018  = (10==LOGICPIN_1001) ? xp__10:xp__11;
  assign LOGICPIN_1047  = LOGICPIN_1001-11>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-11>>31)) && ac_ttf103topTLLLL1Lbar;
  assign LOGICPIN_1101  = ac_ttf104toptLLLL1Lbar && LOGICPIN_1001-12>>31^(LOGICPIN_1001>>31 && !(LOGICPIN_1001-12>>31));
  assign LOGICPIN_1071  = LOGICPIN_1069 || LOGICPIN_1070;
  assign LOGICPIN_1037  = (3==LOGICPIN_1029) ? xp__3:LOGICPIN_1036;
  assign LOGICPIN_1076  = LOGICPIN_1075%31;
  assign LOGICPIN_1155  = (LOGICPIN_1001==2) ? LOGICPIN_1040:xp__2;
  assign LOGICPIN_1027  = (1==LOGICPIN_1001) ? xp__1:LOGICPIN_1026;
  assign ac_alpha_zero  = 0==tt_statereg;
  assign ac_ttf101toptLLLL3Lbar  = 1==tt_statereg;
  assign ac_ttf101topTLLLL3Lbar  = 2==tt_statereg;
  assign ac_ttf102topbar  = 3==tt_statereg;
  assign ac_ttf103toptLLtLLL3Lbar  = 4==tt_statereg;
  assign ac_ttf103toptLLLL1Lbar  = 5==tt_statereg;
  assign ac_ttf103topTLLtLLL3Lbar  = 6==tt_statereg;
  assign ac_ttf103topTLLLL1Lbar  = 7==tt_statereg;
  assign ac_ttf104toptLLLL1Lbar  = 8==tt_statereg;
  assign ac_ttf104topTLLLL1Lbar  = 9==tt_statereg;
  assign ac_ttf104brkLLLL2Lbar  = 10==tt_statereg;
  assign ac_ttf104brkLLLL6Lbar  = 11==tt_statereg;
  assign cxpin_1242  = ac_ttf102topbar && LOGICPIN_1067;
  assign cxpin_1241  = ac_ttf102topbar && (j-12>>31^(j>>31 && !(j-12>>31)) && LOGICPIN_1062);
  assign cxpin_1240  = ac_ttf103toptLLtLLL3Lbar && LOGICPIN_1270;
  assign cxpin_1239  = ac_ttf103toptLLLL1Lbar && LOGICPIN_1270;
  assign cxpin_1238  = ac_ttf103topTLLtLLL3Lbar && LOGICPIN_1270;
  assign cxpin_1237  = ac_ttf103topTLLLL1Lbar && LOGICPIN_1270;
  assign cxpin_1236  = LOGICPIN_1101;
  assign cxpin_1235  = LOGICPIN_1100;
  assign cxpin_1135  = LOGICPIN_1073;
  assign cxpin_1134  = LOGICPIN_1072;
  assign cxpin_1131  = ac_alpha_zero;
  assign cxpin_1130  = ac_ttf104brkLLLL2Lbar;
  assign cxpin_1122  = ac_ttf101toptLLLL3Lbar && LOGICPIN_1005;
  assign cxpin_1121  = ac_ttf101topTLLLL3Lbar && LOGICPIN_1005;
  assign cxpin_1120  = ac_ttf103toptLLtLLL3Lbar && LOGICPIN_1007;
  assign cxpin_1119  = ac_ttf103toptLLLL1Lbar && LOGICPIN_1007;
  assign cxpin_1118  = ac_ttf103topTLLtLLL3Lbar && LOGICPIN_1007;
  assign cxpin_1117  = ac_ttf103topTLLLL1Lbar && LOGICPIN_1007;
  assign cxpin_1111  = ac_ttf102topbar && (j-12>>31^(j>>31 && !(j-12>>31)) && xp__1-xp__0>>7^(((!(xp__1>>7) && xp__0>>7) && xp__1-xp__0>>7) || ((xp__1>>7 && !(xp__0>>7)) && !(xp__1-xp__0>>7))));
  assign cxpin_1110  = ac_ttf103toptLLtLLL3Lbar && LOGICPIN_1283;
  assign cxpin_1109  = ac_ttf103toptLLLL1Lbar && LOGICPIN_1283;
  assign cxpin_1108  = ac_ttf103topTLLtLLL3Lbar && LOGICPIN_1283;
  assign cxpin_1107  = ac_ttf103topTLLLL1Lbar && LOGICPIN_1283;
  assign cxpin_1104  = ac_ttf104toptLLLL1Lbar && LOGICPIN_1005;
  assign cxpin_1103  = ac_ttf104topTLLLL1Lbar && LOGICPIN_1005;

endmodule

Looking carefully at the output, we note that the variable `tt_statereg' has been generated. This variable acts like a program counter. The report file generated by CTOV gives a rough mapping from the values of statereg to line numbers in the C source code.

The second compilation using a RAM to hold the array will be added to this page shortly...