Course pages 2016–17 (still under preparation!)
No. of lectures: 12
Suggested hours of supervisions: 3
Prerequisite courses: Computer Design, C and C++, Computer Systems Modelling
A current-day system on a chip (SoC) consists of several different processor subsystems together with memories and I/O interfaces. This course covers SoC design and modelling techniques with emphasis on power consumption and partition of functionality between hardware and software. We study high-level modelling techniques for rapid architectural exploration and assertion-driven design for correctness. We also look at the semantics of hardware description languages and discuss why or whether they should differ from software languages.
This year, two or three lectures will be replaced with practical classes. Watch out for room change notifications. An industrial-strength System-On-Chip demonstrator is available for those who wish to perform in-depth experiments of their own. A highly cut-down version of it can instead be used to learn the key examinable material. The main languages used are Verilog and C++ using the SystemC library, but basic familiarity with assembly language programming is also required.
- Verilog RTL design with examples. Event-driven simulation with and without delta cycles, basic gate synthesis algorithm and design examples. Structural hazards (memories and multipliers) Pipelining and handshake synthesis. [3 lectures]
- SystemC overview. The major components of the SystemC C++ class library for hardware modelling are covered with code fragments and demonstrations. Queuing/contention delay modelling. Power, energy and layout high-level modelling. [2 lectures]
- Basic bus structures. Bus structure. I/O device structure. Interrupts, DMA and device drivers. Examples. Basic bus bridging.
- ESL + transactional modelling. Electronic systems level (ESL) design. Architectural exploration. Firmware modelling methods. Blocking and non-blocking transaction styles. Approximate and loose timing styles. Examples. [2 lectures]
- ABD: assertions and monitors. Types of assertion (imperative, safety, liveness, data conservation). Assertion-based design (ABD). PSL/SVA assertions. Temporal logic compilation of fragments to monitoring FSM. [2 lectures]
- Engineering aspects: FPGA and ASIC design flow. Cell libraries. Market breakdown: CPU/Commodity/ASIC/FPGA. Further tools used for design of FPGA and ASIC (timing and power modelling, place and route, memory generators, power gating, clock tree, self-test and scan insertion). Dynamic frequency and voltage scaling. [2 lectures]
At the end of the course students should
- be familiar with how a complex gadget containing multiple processors, such as an iPod or Satnav, is designed and developed;
- understand how energy, execution time and silicon area can be traded off;
- understand the hardware and software structures used to implement and model inter-component communication in such devices;
- have basic exposure to SystemC programming and PSL assertions.
* Keating, M. (2011). The Simple art of SoC design. Springer. ISBN 9781441985859.
* OSCI. SystemC tutorials and whitepapers. Download from OSCI http://accellera.org/community/systemc or copy from course web site.
Ghenassia, F. (2010). Transaction-level modeling with SystemC: TLM concepts and applications for embedded systems. Springer.
Eisner, C. & Fisman, D. (2006). A practical introduction to PSL. Springer (Series on Integrated Circuits and Systems).
Foster, H.D. & Krolnik, A.C. (2008). Creating assertion-based IP. Springer (Series on Integrated Circuits and Systems).
Grotker, T., Liao, S., Martin, G. & Swan, S. (2002). System design with SystemC. Springer.
Wolf, W. (2009). Modern VLSI design (System-on-chip design). Pearson Education (4th ed.).