Computer Laboratory

Course pages 2016–17 (still under preparation!)

System-on-Chip Design

Principal lecturer: Dr David Greaves
Taken by: Part II
Past exam questions

No. of lectures: 12
Suggested hours of supervisions: 3
Prerequisite courses: Computer Design, C and C++, Computer Systems Modelling

Aims

Over previous decades, most of the advances in computer performance have arisen from shrinking the physical size of the computer according to Moore’s Law. But when we reached 100 nm transistor size, Dennard Scaling ceased and new computer architectures were required. Semiconductor physicists have provided a world where we can put much more logic on our System On Chip (SoC) that we can conveniently power up at once (Dark Silicon), meaning that application-specific accelerators are increasingly being used. How else does your mobile phone compress motion video without almost immediately flattening the battery?

In this course we examine the basic energy and performance metrics for today’s chip multi-processors (CMPs), caches, busses and DRAM banks and examine the need for, design of and integration of custom accelerators. We briefly visit all of the IP blocks found on a typical SoC, as used in the Raspberry Pi. We look at the future of reconfigurable computing and the role of FPGA in the datacentre.

Examples will assume knowledge of three languages, C, Verilog and assembly language but not require any degree of proficiency in these languages.

Lecture Topics

  • Current-day SoC Tour of IP Blocks. CPU, Co-processor, Cache, Counter/timers, DRAM controller, interrupt dispatcher, I/O devices.

  • Masked versus Configurable Logic. Chip design flow. Field programmable gate array (FPGA) with hardened IP blocks. Zynq example.

  • Energy use in Digital Hardware. Energy and delay tradeoff. Computation versus communication. Switching activity, DVFS, DRAM.

  • Register Transfer Language. RTL simulation and logic synthesis. Structural hazards. Critical Path. Pipelining.

  • High-level Synthesis (HLS). Goals, tool structure, profile-directed feedback, examples.

  • Architectural Exploration. High-level modelling to predict energy use and performance. Transactional modelling.

  • System Specification and Validation. Bus protocols, formal specification, design environments and glue-logic synthesis.

Compared with last year, the following changes have been made: SystemC and PSL de-emphasised. Co-design and device drivers removed. HLS and FPGA emphasised.

Objectives

By the end of the course you should have a working knowledge of the problems faced by today’s hardware engineers designing mobile phones and server blades. You should understand how energy is used in computing systems and the tensions between general-purpose, fixed-function and reconfigurable hardware.

Recommended reading

* Keating, M. (2011). The Simple art of SoC design. Springer. ISBN 9781441985859.
* OSCI. SystemC tutorials and whitepapers. Download from OSCI http://accellera.org/community/systemc or copy from course web site.
Ghenassia, F. (2010). Transaction-level modeling with SystemC: TLM concepts and applications for embedded systems. Springer.
Eisner, C. & Fisman, D. (2006). A practical introduction to PSL. Springer (Series on Integrated Circuits and Systems).
Foster, H.D. & Krolnik, A.C. (2008). Creating assertion-based IP. Springer (Series on Integrated Circuits and Systems).
Grotker, T., Liao, S., Martin, G. & Swan, S. (2002). System design with SystemC. Springer.
Wolf, W. (2009). Modern VLSI design (System-on-chip design). Pearson Education (4th ed.).