Course pages 2011–12
Comparative Architectures
Lecturer: Dr R.D. Mullins
No. of lectures: 16
Prerequisite course: Computer Design
Aims
This course examines the techniques and underlying principles that are used to design high-performance computers and processors. Particular emphasis is placed on understanding the trade-offs involved when making design decisions at the architectural level. A range of processor architectures are explored and contrasted. In each case we examine their merits and limitations and how ultimately the ability to scale performance is restricted.
Lectures
- Introduction.
The impact of technology scaling and market trends.
- Fundamentals of Computer Design.
Amdahl’s law, energy/performance trade-offs, ISA design.
- Advanced pipelining.
Pipeline hazards; exceptions; optimal pipeline depth; branch prediction;
the branch target buffer [2 lectures]
- Superscalar techniques.
Instruction-Level Parallelism
(ILP); superscalar processor architecture [2 lectures]
- Software approaches to exploiting ILP.
VLIW architectures; local and global instruction scheduling techniques;
predicated instructions and support for speculative compiler optimisations.
- Multithreaded processors.
Coarse-grained, fine-grained, simultaneous multithreading
- The memory hierarchy.
Caches; programming for caches; prefetching [2 lectures]
- Vector processors.
Vector machines; short vector/SIMD instruction set extensions;
stream processing
- Chip multiprocessors.
The communication model; memory consistency models;
false sharing; multiprocessor memory hierarchies; cache coherence protocols;
synchronization
- On-chip interconnection networks.
Bus-based interconnects; on-chip packet switched networks
- Special-purpose architectures.
Converging approaches to computer design
Objectives
At the end of the course students should
- understand what determines processor design goals;
- appreciate what constrains the design process and how
architectural trade-offs are made within these
constraints;
- be able to describe the architecture and operation of pipelined
and superscalar processors, including techniques such as
branch prediction, register renaming and out-of-order execution;
- have an understanding of vector, multithreaded and
multi-core processor architectures;
- for the architectures discussed, understand what
ultimately limits their performance and application domain.
Recommended reading
* Hennessy, J. & Patterson, D. (2006). Computer architecture: a quantitative approach. Elsevier (4th ed.) ISBN 978-0-12-370490-0. (3rd edition is also good)