Computer Laboratory – Course material 2008

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System-on-Chip Design

Lecturer: Dr D.J. Greaves

No. of lectures: 12

Prerequisite courses: Specification and Verification II, Computer Design, ECAD, C and C++

Aims

A current-day system on a chip (SoC) consists of several different microprocessor subsystems together with memories and I/O interfaces. This course covers SoC design and modelling techniques with emphasis on architectural exploration, assertion-driven design and the concurrent development of hardware and embedded software. This is the ``front end'' of the design automation tool chain. (Back end material, such as design of individual gates, layout, routing and fabrication of silicon chips is not covered.)

A percentage of each lecture is used to develop a running example. Over the course of the lectures, the example evolves into a System On Chip demonstrator with protocol stacks and device drivers. All code and tools are available online so the examples can be reproduced and exercises undertaken. The main languages used are Verilog and C++ using the SystemC library.

Lectures

Verilog RTL design with examples. Basic RTL to gates synthesis algorithm.
Further examples. Event-driven simulation cycle. Using signals, variables and transactions for component inter-communication.
SystemC overview. Verilog synthesis and high/low-level mapping examples.
High-level modelling in SystemC. Bus and cache structures, DRAM interface. Design exploration.
Transactional modelling (ESL). Electronic systems level design. IP-XACT.
Contemporary ASIC design flow. EDA tools used (timing and power modelling, memory generators, power gating, clock tree, self-test and scan insertion).
Design flow continued. Instruction set simulators, cache modelling and hybrid models.
Assertions and monitors. System Verilog brief tour. PSL/SVA assertions. Temporal logic compilation to FSM. Assertion based design. [2 lectures]
Future languages. Recent developments, lectured as time permits (BlueSpec, H2, Kiwi).
On Chip interconnect. Busses (OPB (BVCI) and AXI). Glue logic synthesis. Transactor synthesis. Network on chip.
Engineering aspects. Scaling, power, logical effort and performance limits.

In addition to these topics, the running example will demonstrate practical aspects of device bus interface design, on chip communication and device control software.

Objectives

At the end of the course students should

be familiar with how a complex gadget containing multiple processors, such as an iPod or Satnav, is designed and developed
understand the hardware and software structures used to implement and model inter-component communication in such devices
be familiar with SystemC and PSL assertions

Recommended reading

* OSCI. SystemC tutorials and whitepapers. Download from OSCI www.systemc.org or copy from course web site.
Ghenassia, F. (2006). Transaction-level modeling with SystemC: TLM concepts and applications for embedded systems. Springer.
Eisner, C. & Fisman, D. (2006). A practical introduction to PSL. Springer (Series on Integrated Circuits and Systems).
Foster, H.D. & Krolnik, A.C. (2008). Creating assertion-based IP. Springer (Series on Integrated Circuits and Systems).
Grotker, T., Liao, S., Martin, G. & Swan, S. (2002). System design with SystemC. Springer.
Wolf, W. (2002). Modern VLSI design (System-on-chip design). Pearson Education. http://www.princeton.edu/wolf/modern-vlsi/

Next: Easter Term 2009: Part Up: Lent Term 2009: Part Previous: Specification and Verification II Contents