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ECAD
Lecturer: Dr S.W. Moore
No. of lectures and practicals: 4 + 8
Prerequisite course: Digital Electronics
This course is a prerequisite for Computer Design and System-on-Chip Design (Part II).
Aims
This course aims to introduce electronic computer aided design (ECAD) with a particular emphasis on the Verilog hardware description language (HDL). The course covers eight lectures of material but four of the lectures have been replaced by an interactive tutor system to teach Verilog (the Intelligent Verilog Compiler, or IVC). The IVC will be used for the first two laboratory sessions and completed as homework. The material the IVC covers is a prerequisite for the remaining seven practical sessions.
Lectures
- Introduction and motivation.
Current technology, technology trends, ECAD trends, challenges.
- Logic modelling, simulation and synthesis.
Logic value and delay modelling. Discrete event and device
simulation. Automatic logic minimization.
- Chip, board and system testing.
Production testing, fault models, testability, fault coverage,
scan path testing.
- Verilog systems design. Practicalities of mapping Verilog descriptions of hardware (including a MIPS processor) onto an FPGA board. Introduction of SystemVerilog constructs not covered by IVC. Tips and pitfalls when generating larger modular designs.
On-Line Learning Component: Interactive Verilog Compiler
- The interactive Verilog compiler (IVC) teaches the synthesizable
subset of Verilog which is required to complete the laboratory
sessions.
Objectives
At the end of the course students should
- be able to design, prototype and debug circuits using Verilog targeted
at programmable gate arrays (FPGA)
- understand circuit simulation, synthesis and testing concepts
- appreciate hardware/software codesign
Recommended reading
* Harris, D. & Harris, S. (2007). Digital design and computer architecture: from gates to processors. Morgan Kaufmann.
Pointers to sources of more specialist information are included in the lecture notes and on the associated course web page.




Next: Group Project Up: Michaelmas Term 2008: Part Previous: Concurrent Systems and Applications Contents