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Comparative Architectures
Lecturer: Dr R.D. Mullins
No. of lectures: 16
Prerequisite course: Computer Design
Aims
This course examines the techniques and underlying principles that are used to design high-performance computers and processors. Particular emphasis is placed on understanding the trade-offs involved when making design decisions at the architectural level. A range of processor architectures are explored and contrasted. In each case we examine their merits and limitations and how ultimately the ability to scale performance is restricted.
Lectures
- Introduction.
The impact of technology scaling, market trends and application
characteristics. Power and performance metrics. Environmental impact.
- Review.
Instruction-set principles; the scalar pipeline
- Overview of architectural techniques.
Classification of approaches; examples and pitfalls; Amdahl's law
- Advanced Pipelining.
Pipeline hazards; exceptions; branch prediction; avoiding branches;
fetch issues; trace cache;
limitations of pipelining and optimal pipeline depth [2 lectures]
- Superscalar techniques.
Instruction-Level Parallelism (ILP); static and dynamic scheduling;
register renaming; load/store instruction ordering;
advanced speculation techniques; example microarchitectures [2 lectures]
- Software approaches to exploiting ILP.
VLIW architectures; dynamic binary code translation;
exploiting compiler hints
- Multithreaded processors.
Coarse-grained, fine-grained, SMT
- The memory hierarchy.
Caches; programming for caches; prefetching;
software managed memories; main memory [3 lectures]
- Vector processors.
Vector machines; short vector/SIMD instruction set extensions;
stream processing
- Chip multiprocessors.
Examples of multi-core processors;
Memory, interconnect and programming challenges;
performance limits
- Special-purpose architectures. Converging approaches to computer
design
- Review and current developments
Objectives
At the end of the course students should
- understand what determines processor design goals.
- appreciate what constrains the design process and how
architectural trade-offs are made within these
constraints.
- be able to describe the architecture and operation of pipelined
and superscalar processors, including techniques such as
branch prediction, register renaming and out-of-order execution.
- have a basic understanding of vector, multithreaded and
multi-core processor architectures.
- for the architectures discussed, understanding what
ultimately limits their performance and application domain.
Recommended reading
* Hennessy, J. & Patterson, D. (2006). Computer architecture: a quantitative approach. Elsevier (4th ed.) ISBN 978-0-12-370490-0. (3rd edition is also good)




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