CONfigurable Transceiver Energy uSage Toolkit (CONTEST) allows the characterisation of the energy consumption of the physical layer of optical transceivers including line coding, frame alignment, channel bonding, serialisation and deseralisation, clock/data recovery and clock generation.
Power consumption of networking equipment are under increasing scrutiny, particularly as network end points are moving on-chip in the latest generation of SoC processors. Although ultra-low energy silicon photonic components have been demonstrated, these components and front end drivers only consume a small proportion of total serial transceiver power. Hence, major reductions in optical transceiver power can only be obtained with attention to the physical layer circuits of which serialisation and deserialisation are the largest component. In addition, burst mode transceivers are required both for power gating and to take advantage of future optical switching systems.
To facilitate continued work in this field we provide CONTEST, promoting direct comparison by enabling other researchers to reproduce our results thereby permitting meaningful comparison.
The toolkit contains a combination of source code files for each basic transceiver building block design (Verilog/HSpice)and a set of configuration scripts (Perl/Tcl) for stimuli generation, synthesis, simulation and power analysis using a standard CMOS technology process library.
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If you use this toolkit in your own research, please cite the following paper: Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, "Power Optimized Transceivers for Future Switched Networks," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.PP, no.99, pp.1,1, 0 doi: 10.1109/TVLSI.2013.2283300 Publisher URL pre-print
Contacts Details:
Yury Audzevich (Computer Laboratory, University of Cambridge)
Philip Watts (Dept. of Electronic and Electrical Engineering, UCL)
Andrew W. Moore (Computer Laboratory, University of Cambridge)
This work was supported in part by the EPSRC program grants, INTelligent Energy awaRe NETworks (INTERNET) and UNLocking the capacity of Optcial Communications (UNLOC) projects and an EPSRC Career Acceleration Research Fellowship award to Philip Watts. Additionally, this research is sponsored by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory (AFRL), under contract FA8750-11-C-0249.
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