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Department of Computer Science and Technology

Part IA CST

 

Course pages 2023–24

Digital Electronics

Principal lecturer: Dr Ian Wassell
Taken by: Part IA CST
Term: Michaelmas
Hours: 12 (12 lectures+ 4 practical classes)
Format: In-person lectures
Suggested hours of supervisions: 3
This course is a prerequisite for: ECAD and Architecture Practical Classes, Introduction to Computer Architecture, Operating Systems
Exam: Paper 2 Question 1, 2
Past exam questions, Moodle, timetable

Aims

The aims of this course are to present the principles of combinational and sequential digital logic design and optimisation at a gate level. The use of n and p channel MOSFETs for building logic gates is also introduced.

Topics

  • Introduction. Semiconductors to computers. Logic variables. Examples of simple logic. Logic gates. Boolean algebra. De Morgan’s theorem.
  • Logic minimisation. Truth tables and normal forms. Karnaugh maps. Quine-McCluskey method.
  • Binary adders. Half adder, full adder, ripple carry adder, fast carry generation.
  • Combinational logic design: further considerations. Multilevel logic. Gate propagation delay. An introduction to timing diagrams. Hazards and hazard elimination. Other ways to implement combinational logic.
  • Introduction to practical classes. Prototyping box. Breadboard and Dual in line (DIL) packages. Wiring.
  • Sequential logic. Memory elements. RS latch. Transparent D latch. Master-slave D flip-flop. T and JK flip-flops. Setup and hold times.
  • Sequential logic. Counters: Ripple and synchronous. Shift registers. System timing - setup time constraint, clock skew, metastability.
  • Synchronous State Machines. Moore and Mealy finite state machines (FSMs). Reset and self starting. State transition diagrams. Elimination of redundant states - row matching and state equivalence/implication table.
  • Further state machines. State assignment: sequential, sliding, shift register, one hot. Implementation of FSMs.
  • Introduction to microprocessors. Microarchitecture, fetch, register access, memory access, branching, execution time.
  • Electronics, Devices and Circuits. Current and voltage, conductors/insulators/semiconductors, resistance, basic circuit theory, the potential divider. Solving non-linear circuits. P-N junction (forward and reverse bias), N and p channel MOSFETs (operation and characteristics) and n-MOSFET logic, e.g., n-MOSFET inverter. Power consumption and switching time problems problems in n-MOSFET logic. CMOS logic (NOT, NAND and NOR gates), logic families, noise margin.

Objectives

At the end of the course students should

  • understand the relationships between combination logic and boolean algebra, and between sequential logic and finite state machines;
  • be able to design and minimise combinational logic;
  • appreciate tradeoffs in complexity and speed of combinational designs;
  • understand how state can be stored in a digital logic circuit;
  • know how to design a simple finite state machine from a specification and be able to implement this in gates and edge triggered flip-flops;
  • understand how to use MOSFETs to build digital logic circuits.

Recommended reading

* Harris, D.M. and Harris, S.L. (2013). Digital design and computer architecture. Morgan Kaufmann (2nd ed.). The first edition is still relevant.
Katz, R.H. (2004). Contemporary logic design. Benjamin/Cummings. The 1994 edition is more than sufficient.
Hayes, J.P. (1993). Introduction to digital logic design. Addison-Wesley.

Books for reference:

Horowitz, P. and Hill, W. (1989). The art of electronics. Cambridge University Press (2nd ed.) (more analog).
Weste, N.H.E. and Harris, D. (2005). CMOS VLSI Design - a circuits and systems perspective. Addison-Wesley (3rd ed.).
Mead, C. and Conway, L. (1980). Introduction to VLSI systems. Addison-Wesley.
Crowe, J. and Hayes-Gill, B. (1998). Introduction to digital electronics. Butterworth-Heinemann.
Gibson, J.R. (1992). Electronic logic circuits. Butterworth-Heinemann.