|| ARM+FPGA based Rugby clock
In this lab you will have to put together the various things done
in the previous practicals to make an electronic clock that picks up
the Rugby time signal (rebroadcast in the Intel Lab in infrared).
Copy your previous Lab 5 to a new
directory, and open the project in Quartus. You now need the Verilog
file (main.v) from Lab 3 that
demodulates the IR signal. You should rename this to demod.v, add it
to the project, and edit it to create a module (called demod) that
takes as inputs CLK and the IR signal, and outputs a 3 bit value
containing bit A, the new minute bit, and a bit that changes state
when a new frame arrives.
Change the original main.v for lab 5 so that it does the following
things in turn:
- Read from address 0 of the dual-ported RAM into a 16-bit
register that feeds the LED display module.
- Write to address 1 of the dual-ported RAM the value returned from
the demod module.
A state machine which reads and writes over several clocks would be
an idea - reading on one clock and writing the next is very unreliable.
You may also want to make your code display the output of the demod
module on the LED bar graph for debugging purposes.
For the ARM, you should write some code that looks at address 4 in
the dual-ported RAM each time the new frame marker changes (every
location is mapped to the nearest 32-bit location, so address 4 is the second
32-bit word). It should use the information to decode the signal from the Rugby
Clock, and display hours and minutes on the LED Clock Display. Information on
the signal format is available below:
If you finish this lab early, you might like to try the following bonus
exercise. You don't get anything for this except a warm fuzzy feeling and the
respect of the other students. Adapt the ARM code so that it outputs the
current time on the serial port when the minute changes. This could be used to
set the clock on a computer accurately. You will probably need to adapt some
code from lab 4 for this, and you will have to be careful not to make the loop
longer than a second, otherwise you will miss bits from the Rugby signal. If
you get this working and are still feeling confident, you could adapt your code
further to also output the date, either as a number (as in 20/08/04) or in
words (20th August 2004).
- It is probably a good idea to start off with a counter that counts
seconds (e.g. every time the new frame bit from the FPGA changes), that
resets on a new minute marker (see information on the signal
format). This could then be used to write data away in a location
reserved for that second. At the end of a minute, you can write code
that will scan this area of memory, picking out the required
- You will probably find UART_TXD_DECIMAL, UART_TXD_STR and
UART_TXD_HEX useful to debug parts of your code by outputting the
contents of registers, but to do this you will have to keep r0-3 free. You
should try to do this from the start.
- The data from the MSF signal is in binary-coded decimal (BCD) so you will
not need to do any binary-to-decimal conversion; you will just need to extract
the bits containing the time.
- You will need to assert dp_we when you want to write to the
memory, and de-assert it when you want to read. In lab 5 dp_we is
assigned 0, so you will have to change this.
- Comment on the hardware/software divide. How much could you
reasonably move from the hardware into the software and vice-versa?
- Estimate the worst case total delay between the clock in Rugby and
the output on your LED display. Also, how long does it take your clock in the
worst case to synchronise with Rugby?
- The LED display should display the current time in hours and
minutes and the seconds should be indicated by flashing the dot. Every
minute the value should be updated - some (fewer than 1 in 5)
receiving errors are allowed.
- As an optional extra, you might like to display the seconds in
binary on the LED bar graph.
- You must give a live demonstration of your solution.
- Your ARM and Verilog code must be cleanly formatted and commented.
- Answers to the questions for the workshop must be added to the end
of your code.
- The following header must be added to all Verilog code submitted:
// ECAD+Arch Workshop 6 - ARM+FPGA based Rugby clock
// Your name
// Your college
// Your email address
- and the following header must be added to all assembly code submitted:
; --=== ECAD and Architecture Lab 6 ===--
; Your name
; Your email address
- There is no need to submit code from previous labs if you have not changed it in this lab.
- Show your work to one of the demonstrators (on screen or
paper). They will award you with a tick if the work is up to
- Print out your final work and add it to your portfolio to be
submitted as instructed in the Head of Department notice.