Principal lecturer: Dr Simon Moore
Taken by: Part IB

Syllabus

# Handouts

The lecture notes are handed out at the first lecture. Further copies should be available from Student Admin. (student-admin@cl.cam.ac.uk). A PDF is also available from the cam.ac.uk domain only (the download incorporates the errata below).

# Errata

Lecture 1, slide 1-9, some of the the output wires and module names were incorrect:

```    xor     xorR(red_in,red_out,red_out);
inv     invA(amber_in,amber_out);
and     andG(green_in,red_out,green_out);
```

Lecutre 3, slide 3-4, module debouncea needs to be corrected to (a) help the latest version of Quartus synthesis it correctly (!) and (b) to avoid looking at the first sample since it might go metastable.

```module debouncea(clean_pb, pb, clk);

output  clean_pb;
input   pb,clk;

// parametarised sample rate and number of samples
parameter debounce_sample_rate_bits=15;
parameter debounce_samples=7;

reg [debounce_sample_rate_bits:0] dly;
reg [debounce_samples:0] samples;
reg clean_pb;

always @(posedge clk) begin
dly <= dly + 1;
if(dly==0) begin
samples[debounce_samples:1] <= samples[debounce_samples-1:0];
samples[0] <= pb;
end
if(|samples[debounce_samples:1]==0) clean_pb<=0;
if(&samples[debounce_samples:1]==1) clean_pb<=1;
end

endmodule
```

Lecture 5, slide 5-19, the RS flip-flop has the inputs the wrong way around.

An alternative example of 1-hot encoding (replacing the example at the bottom of slide 3-10:

```reg [3:0] four_states;
wire red   = four_states[0] || four_states[1];
wire amber = four_states[1] || four_states[3];
wire green = four_states[2];

always @(posedge clk or posedge reset)
if(reset)
four_states <= 4'b0001;
else
four_states <= {four_states[2:0],four_states[3]};  // rotate bits
```

The old version of lecture 4 was accidently included in the handout. The replacement lecture was handed out at the beginning of lecture 1, and spare copies are available via Student Admin. (in the Computer Lab.).