NEXT (Basic Physics)
Part II CST SoC D/M Slide Pack 2 (Power)
Power, Performance and Technology
Chip Dissipation and Delay
Detailed Delay Model.
Detailed Power Model.
Dynamic Frequency and Voltage Scaling Example (DVFS)
Silicon Power and Technology
Semi-Custom Design (repeated slide)
90 Nanometer Gate Length.
Deep submicron and Dark Silicon
Voltage Operating Point Adjustment
Power Saving Techniques
Save Power 1: Dynamic Clock Gating
Save Power 2: Dynamic Supply Gating
Save Power 3: Dynamic Frequency Scaling
Save Power 4: Dynamic Voltage and Frequency Scaling (DVFS)
Example 3 - Static and Dynamic Power Tradeoff