Save Power 3: Dynamic Frequency Scaling

Frequency scaling means adjusting the clock frequency to a subsystem.

Frequency scaling is software controlled by updating divider ratios. Adjustment can be instant, but reconfiguring PLL may have inertia (say 1 millisecond for analog PLL). Let's adjust the clock frequency (while keeping supply VCC constant for now). Does this help ?

Compare dynamic frequency adjustment with with clock and supply gating:

	Clock Gating	Supply Gating	Frequency Adjustment
Control:	automatic	various	software
Granularity:	register / FSM	larger blocks	macroscopic.
Clock Tree:	mostly free runs	turned off	slows down.
Response time:	instant	2 to 3 cycles	instant (or ms if PLL adjusted)
Proportionally vary voltage:	not possible	n/a	yes.

Two potential strategies (Zeno: Tortoise v Achilles):

1. Compute quickly and then halt.
2. Compute more slowly and finish just in time.

To compute quickly and halt we need a higher frequency clock but consume the same number of active cycles.

So the work-rate product, af, unchanged, so no power difference ? No.

First issue: un-stopped regions (clock trees etc.) consume power proportional to f.

Second issue: A fixed Vdd must be set to support the fastest clock frequency in use.

Solution: adjust the supply voltage as we adjust the clock frequency (DVFS)