Course pages 2015–16
This course aims to provide an introduction to parallel computing with a particular focus on chip multiprocessors. The course begins by examining the motivation for the current shift away from uniprocessors. It explores the basics of parallel algorithm design, approaches to parallel programming and the architecture of modern chip-multiprocessors. The final seminar explores the challenges in attempting to scale chip-multiprocessor designs beyond the modest number of cores seen in today's designs.
- Trends in microprocessor architecture.
- Introduction to parallel computing.
- Parallel algorithms.
- Chip multiprocessor architecture and cache coherency [2 seminars].
- Transactional memory.
- On-chip interconnection networks.
- Manycore research issues.
On completion of this module students should:
- understand the reasons for the shift from wide-issue superscalar to multi-core processors;
- appreciate the challenges involved in exploiting parallel processors and their limits;
- be familiar with a range of approaches to parallel programming based on both shared-memory and message-passing models;
- understand the cache-coherency and transactional memory systems that support shared-memory programming in multiprocessors;
- have a clear understanding of the wide range of possible on-chip interconnection network designs;
- be able to discuss the challenges in exploiting a large number (possibly hundreds) of processing cores on a single chip.
To complete two paper reviews and write a short survey paper.
Each seminar will consist of a short lecture, reading club and student presentations.
Assessments will be set and marked by the course lecturer.
- Test (50%)
- Coursework and ticks (50%)
(10% for each review, 20% for survey paper, 10% for participation)
Final module mark will be percentage.
Most of the reading for this course will be in the form of the selected papers each week. However, the following may be useful background reading to refresh your knowledge from undergraduate courses:
Culler, D.E. & Singh, J.P. (1999). Parallel computer architecture: a
hardware/software approach. Morgan Kaufmann, ISBN 1-55860-343-3.
Grama, A, Anshul, G., Karypis, G. & Kuman, V. (2004). Introduction to parallel computing. Addison-Wesley (2nd ed.).
Hennessy, J.L. & Patterson, D.A. (2006). Computer architecture: a quantitative approach. Morgan Kaufmann (4th ed.).
Herlihy, M. & Sahvit, N. (2008). The art of multiprocessor programming. Morgan Kaufmann. ISBN: 978-0-12-370591-4.
Olukotun, K., Hammond, L. & Laudon, J. (2007). Chip multiprocessor architecture. Morgan Claypool. ISBN: 978-1598291223.
A list of papers will also be provided for discussion at each seminar. The complete reading list will be available from the course web page.
All students should have a good knowledge of the material presented in the Hennessy and Patterson book. Chapter 4 in particular is essential reading before the course begins.
R05 Chip Multiprocessors cannot be taken in conjunction with L18 Automated Reasoning or L108 Category Theory and Logic in 2012-13. Students wishing to take E4F8 Image Coding and Image Processing with R05 should note that E4F8 is taught in the Department of Engineering (Map) which is approximately 2 miles from the Computer Laboratory by bicycle.