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Shortcomings of Verilog and VHDL (for H/L Synthesis).

Too much is explicit in the source Verilog text:

Although highly-concurrent, no indication of what aspects of the concurrency are important.

Cannot use software design paradigms, such as sending a thread between components with implied< flow control.

18: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.