Course pages 2012–13
No. of lectures: 12
Suggested hours of supervisions: 3
Prerequisite courses: Computer Design, C and C++, Computer Systems Modelling
A current-day system on a chip (SoC) consists of several different processor subsystems together with memories and I/O interfaces. This course covers SoC design and modelling techniques with emphasis on architectural exploration, assertion-driven design and the concurrent development of hardware and embedded software. This is the “front end” of the design automation tool chain. (Back end material, such as design of individual gates, layout, routing and fabrication of silicon chips is mentioned but not examinable.)
A percentage of each lecture is used to develop a running example. Over the course of the lectures, the example evolves into a System On Chip demonstrator with CPU and bus models, device models and device drivers. All code and tools are available online so the examples can be reproduced and exercises undertaken. The main languages used are Verilog and C++ using the SystemC library.
- Verilog RTL design with examples. Event-driven simulation with and without delta cycles, basic gate synthesis algorithm and design examples. Structural hazards (memories and multipliers) Pipelining and handshake synthesis. [3 lectures]
- SystemC overview. The major components of the SystemC C++ class library for hardware modelling are covered with code fragments and demonstrations. Queuing/contention delay modelling. Power, energy and layout high-level modelling. [2 lectures]
- Basic bus structures. Bus structure. I/O device structure. Interrupts, DMA and device drivers. Examples. Basic bus bridging.
- ESL + transactional modelling. Electronic systems level (ESL) design. Architectural exploration. Firmware modelling methods. Blocking and non-blocking transaction styles. Approximate and loose timing styles. Examples. [2 lectures]
- ABD: assertions and monitors. Types of assertion (imperative, safety, liveness, data conservation). Assertion-based design (ABD). PSL/SVA assertions. Temporal logic compilation of fragments to monitoring FSM. [2 lectures]
- Engineering aspects: FPGA and ASIC design flow. Cell libraries. Market breakdown: CPU/Commodity/ASIC/FPGA. Further tools used for design of FPGA and ASIC (timing and power modelling, place and route, memory generators, power gating, clock tree, self-test and scan insertion). Dynamic frequency and voltage scaling. [2 lectures]
- Higer-level approaches Only presented if time permits. Non-examinable. Co-design, co-synthesis and custom processor synthesis. IP-XACT, Kiwi HLS. Transactor synthesis.
In addition to these topics, the running example will demonstrate a few practical aspects of device bus interface design, on chip communication and device control software. Students are encouraged to try out and expand the examples in their own time.
At the end of the course students should
- be familiar with how a complex gadget containing multiple processors, such as an iPod or Satnav, is designed and developed;
- understand the hardware and software structures used to implement and model inter-component communication in such devices;
- have basic exposure to SystemC programming and PSL assertions.
* OSCI. SystemC tutorials and whitepapers. Download from OSCI http://www.systemc.org or copy from course web site.
Ghenassia, F. (2010). Transaction-level modeling with SystemC: TLM concepts and applications for embedded systems. Springer.
Eisner, C. & Fisman, D. (2006). A practical introduction to PSL. Springer (Series on Integrated Circuits and Systems).
Foster, H.D. & Krolnik, A.C. (2008). Creating assertion-based IP. Springer (Series on Integrated Circuits and Systems).
Grotker, T., Liao, S., Martin, G. & Swan, S. (2002). System design with SystemC. Springer.
Wolf, W. (2009). Modern VLSI design (System-on-chip design). Pearson Education (4th ed.).