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Part II CST SoC D/M Slide Pack 6 (Tools/Tech/Eng)
SoC Engineering and Associated Tools
Static Timing Analyser Tool
RAM Macrocell Compiler Tool
Test Program Generator Tool
Scan Path Insertion and JTAG standard test port.
Architectural Design Exploration
H/W to S/W Interfacing Techniques
Conservation Cores Approach
H/W Design Partition
Chip Types and Classifications
IC Taxonomy
Semi-custom (cell-based) Design Approach
Cell Library Tour
Gate Arrays and Field-Programmable Logic.
FPGA - Field Programmable Gate Array
PALs and CPLDs
H/W versus S/W Design Partition Principles
An old partitioning example: An external RS-232/POTS Modem.
Partitioning example: A Bluetooth Module.
ASIC costing.
Structured ASIC
Xilinx Zynq Super FPGA