ECAD and Architecture Practical Classes
Exercises
The ticking criteria for this lablet is to complete the following two exercises to the ticker's satisfaction. Any suggested implementation may be ignored in favour of another, sensible approach.
You may wish to refer to the SystemVerilog Cheat Sheet.
Exercise 1 - Synchronisation
Behaviour
Create a synchronisation module for use in the second exercise. The module should accept a 1-bit asynchronous input (and a clock signal) and present it as a 1-bit synchronous output.
Implementation Advice
In Quartus, click File | New and select SystemVerilog HDL File in the dialog that appears. Click OK.
A useful formatting convention for modules is:
Declare a new module with the interface (inputs / outputs) described above. Note that when saving a file, it is conventional to give it the name of its root module. Define the module by implementing the specified functionality after reading the following discussion.
Discussion
Consider an asynchronous signal - one independent of the clock - that we wish to assign to a register. If the signal changes close to a clock edge, the register may enter a metastable state: the output signal may not be digital, although electrical effects will cause digitisation after some delay. Shifting the input through an additional register should add sufficient latency for the signal to settle to a synchronous, digital value.
Signals generated by mechanical systems, such as buttons, are not only asynchronous but may also exhibit a bouncing property over multiple clock cycles: the raw signal alternates (bounces) and eventually converges. The tPad push-buttons are debounced using circuitry on the board; the resulting signal still requires synchronisation to the system clock.