Computer Laboratory

ECAD and Architecture Practical Classes


Modelsim is used to simulate SystemVerilog. It produces text output when $display statements are executed in simulation and can display waveforms (a graphs with time on the X-axis and signal states on the Y-axis) as the system simulates.

You can download the Altera Modelsim Starter Edition if you wish to install it on your own machine.

Modelsim is introduced in Lab 1 - Simulation.