Computer Laboratory

Course material 2010–11

Computer Design

Lecturer: Dr S.W. Moore

No. of lectures: 22 (including 4 via a web-based tutor)

Prerequisite course: Digital Electronics

This course is a prerequisite for the Part II courses Comparative Architectures and System-on-Chip Design.


The aims of this course are to introduce a hardware description language (Verilog) and computer architecture concepts in order to design computer systems. This is an amalgam of the former ECAD and Computer Design courses.

There are 18 lectures which cover design with hardware description languages, computer architecture and then computer implementation. A web based tutor (equivalent of 4 lectures) is used to teach much of the Verilog hardware description language.


  • Introduction and motivation. Current technology, technology trends, ECAD trends, challenges.

  • Logic modelling, simulation and synthesis. Logic value and delay modelling. Discrete event and device simulation. Automatic logic minimization.

  • Verilog systems design. Practicalities of mapping Verilog descriptions of hardware (including a MIPS processor) onto an FPGA board. Introduction of SystemVerilog constructs not covered by IVC. Tips and pitfalls when generating larger modular designs.

  • Chip, board and system testing. Production testing, fault models, testability, fault coverage, scan path testing, simulation models.

  • Historical perspective on computer architecture.

  • Early instruction set architecture. EDSAC versus Manchester Mark I.

  • Build your first computer. Implement a Manchester Baby machine in Java and Verilog.

  • RISC machines. Introduction to RISC processor design and the MIPS instruction set.

  • MIPS tools and code examples.

  • CISC machines and the Intel x86 instruction set.

  • Java Virtual Machine.

  • Memory hierarchy. Virtual memory and caching.

  • Simulating a MIPS processor.

  • Pipelining and data paths.

  • Implementation of a MIPS processor. Verilog implementation of a MIPS processor subset.

  • Internal and external communication.

  • Introduction to many-core processors.

  • Data-flow machines. Future directions.

On-Line Learning Component: Interactive Verilog Compiler

  • The interactive Verilog compiler (IVC) teaches the synthesizable subset of Verilog which is required to complete the laboratory sessions.


At the end of the course students should

  • be able to read assembler given a guide to the instruction set and be able to write short pieces of assembler if given an instruction set or asked to invent an instruction set;

  • understand the differences between RISC and CISC assembler;

  • understand what facilities a processor provides to support operating systems, from memory management to software interrupts;

  • understand memory hierarchy including different cache structures;

  • appreciate the use of pipelining in processor design;

  • understand the communications structures, from buses close to the processor, to peripheral interfaces;

  • have an appreciation of control structures used in processor design;

  • have an appreciation of how to implement a processor in Verilog.

Recommended reading

* Harris, D.M. & Harris, S.L. (2007). Digital design and computer architecture: from gates to processors. Morgan Kaufmann.

Recommended further reading:

Hennessy, J. & Patterson, D. (2006). Computer architecture: a quantitative approach. Elsevier (4th ed.). ISBN 978-0-12-370490-0. (Older versions of the book are also still generally relevant.)
Patterson, D.A. & Hennessy, J.L. (2004). Computer organization and design. Morgan Kaufmann (3rd ed., as an alternative to the above). (2nd ed., 1998, is also good.)

Pointers to sources of more specialist information are included in the lecture notes and on the associated course web page.