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Part II CST SoC D/M Slide Pack 8 (High-Level Synthesis)
High-level Design Capture and Synthesis
High-level Design Capture and Synthesis
Spirit IP XACT
IP XACT Tool Flow
High-Level Synthesis
High-Level Synthesis
Higher level: Behavioural or Logical ?
Behavioural Expression
Behavioural Expression
Beyond Pure RTL: Behavioural descriptions of hardware.
More-advanced behavioural specification:
Static and Dynamic Scheduling
Synopsys Behavioural Compiler
Shortcomings of Verilog and VHDL (for H/L Synthesis).
Motivations to do better.
Channel Communications
H/W Synthesis from C and other Programming Languages.
Kiwi : Compiling Concurrent Programs to Hardware
State charts and Graphical `languages'
Behavioural H/L Synthesis Summary
Synthesis from Declarative Specifications
Synthesis from Declarative Specifications
Synthesis from Formal Specification
FOR CORRECT TYPESETTING PLEASE SEE PREVIOUS SLIDE
Refinement from a specification to implementation.
Rule-based hardware generation (BlueSpec)
Synthesis from Rules (SAT-based idea).