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Rule-based hardware generation (BlueSpec)

In the last two years, Bluespec System Verilog has successfully raised the level of abstraction in RTL design in the industry.

»LINK: Small Examples First basic example: two rules: one increments, the other exits the simulation. This example looks very much like RTL: provides an easy entry for hardware engineers.
module mkTb (Empty);

   Reg#(int) x <- mkReg (23);

   rule countup (x < 30);
      int y = x + 1;
      x <= x + 1;
      $display ("x = %0d, y = %0d", x, y);

   rule done (x >= 30);
      $finish (0);

endmodule: mkTb

Second example uses a pipeline object that could have aribtrary delay. Sending process is blocked by implied handshaking wires (hence less typing than Verilog) and in the future would allow the programmer or the compiler to retime the implementation of the pipe component.

module mkTb (Empty);

   Reg#(int) x    <- mkReg ('h10);
   Pipe_ifc  pipe <- mkPipe;

   rule fill;
      pipe.send (x);
      x <= x + 'h10;

   rule drain;
      let y = pipe.receive();
      $display ("    y = %0h", y);
      if (y > 'h80) $finish(0);

But, behavioural expressing using a conceptual thread is also useful to have!

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.