NEXT (Shortcomings of Verilog and VHDL (for H/L Synthesis).)
Synopsys Behavioural Compiler
... was an advanced (for the late 90's) compiler that extended RTL synthesis semantics.
- Provided compile-time loop unrolling,
- Operations on variables freely moved between clock cycles,
- Additional cycles to overcome hazards (user's clock is called a `super state'),
- Provided temporally floating I/O with variable pipelining between ports.
Existing RTL paradigms not preserved within the same source file: existing syntax has new meaning.
Ulitmately, it seems designers felt they had lost control over detailed structure in critical places.
»Synopsys Behavioural Compiler Tutorial
- Understanding Behavioral Synthesis, A Practical Guide to High Level Design by John P Elliott;
Kluwer Academic Publishers ISBN 0-7923-8542-X
- Behavioral Synthesis, Digital System Design Using the Synopsys Behavioral Compiler by David W. Knapp, Prentice Hall, ISBN 0-13-569252-0