Schedule - Hardware
All deliverables are due no later than
|Implement four port
||Email summarizing your progress getting the tools set up:
Simulation, Synthesis, and running tests on the hardware.
||Operational input arbiter (submit archive of project directory)
|9AM Friday 23-Oct
||1. Working four-port non-learning switch (bit file and archive of
2. First version of the Hardware Design document (architecture)
3. Test summary
|Implement IP router,
software integration and testing of IP router
||1. Implement basic packet counter registers
2. Add a written/drawn design of the Output Port Lookup module to your
||1. Verification section of the Hardware Design Document
2. Ability to forward packets to/from software
3. Verify and update TTL/IP checksum
4. HW+SW: Initial Proposal of Advanced Feature
||1. Verify the MAC address of all received packets
2. Lookup destination IP addresses in a lookup table. Forward matching
packets to CPU instead of processing in normal forwarding path.
3. Interoperability testing section added to design document
4. HW+SW: Final Proposal of Advanced Feature
||1. Implement remaining functionality, including routing and ARP
||1. Email update on progress (1 for each team)
2. A tarball of your design (no dump files or packet_data directories
Development and Router Interoperation
||2 weeks effective (*)
||1. Email update on progress (1 for each team).
2. Updated hardware design document (including advanced feature
||1. tar.gz file of your working directory including src and verif.
(but no dump files, please!)
2. Updated Hardware Design Document with your added functionality.
(*) You are expected to commit the equivalent of one in-term week worth of
work to this module over the Christmas/New-Year vacation. No less than 10
Hours between the 3rd of December, 2009 and the deadline 10th of January,