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Subsections

Synthesisable Language Subset

This chapter will explain the synthesisable subset of C# supported by Kiwic.

New is supported in kiwic, provided it is called only from constuctors or once and for all on the main threads before they enter an infinite loop.

FAQ

Q. Why is the reset input not used?

A. The reset net is disconnected unless you indeed add

 -resets synchronous
or
 -resets asynchronous       

or change this xml line in the file /distro/lib/recipes/kiwic00.rcp

 <defaultsetting> resets none </defaultsetting>

Q. Why does the type of the output result end up as: reg [31:0] FIFO_FIFO2_result; instead of reg FIFO_FIFO2_result; ?

A. In Verilog, integers are signed and registers are not. You can alter this by adjusting the definition of result. Recent Verilog standards also allow signed registers to be defined.

Q. I thought I would have a go at synthesizing the ... However, the Verilog finish statement gets in the way. Should there really be a finish command in synthesizable Verilog?

A. If the main entry point to the C# program allows its thread to exit then a finish will be put in the output code. This is indeed not synthesisable. Quite often one wants the program to exit when run native but not when synthesised. The solution to this is to place the main body of the program in a subroutine that is called from the Main method (ie the entry point). The same subroutine is also called from a second method where it is enclosed in an infinite while loop. This second method can then be named as the root to kiwic and this will avoid a finish statement in the generated code.

Suppressing the default operation on main thread exit statement can be controlled with a command line flag -finish set to true or false.

Another solution is to mark up the main body subroutine with the Kiwi.Remote attribute. This places it in an infinite loop, and adds handshaking wires to start and stop its execution.

Accessing Simulation Time

The Kiwi library declares a static variable called tnow. During compilation are replaced with references to the appropriate runtime mechanism for access to the current simulation time. For instance, the following line

   Console.WriteLine("Start compute CRC of result at {0}\n", Kiwi.tnow);
becomes
   $display("Start compute CRC of result at %t\n", $time);
when output as Verilog RTL.


next up previous contents index
Next: Orangepath Synthesis Engines Up: Kiwi kiwic Compiler Users' Previous: C# Attributes   Contents   Index
David Greaves 2011-03-31