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Introduction
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Kiwi / KiwiC Compiler
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Preface
Index
Contents
Asymptotic Background Motivation for FPGA Computing
Download and License
Warranty
Scientific Users' Guide
Kiwi Substrate
Console and LCD stdout I/O and LED GPIO
Run-time Exception Handler
DRAM
Watchpoints and Start/Stop Control
Framestore
Profiling
Installation and Easy Get Started
Get Started (Mono on Linux)
Getting A K-Distro Binary Distribution
Using A K-Distro Binary Distribution
Kiwi Supported Language Subset Limitations and Style Guide
General CSharp Language Features and Kiwi Coding Style
Supported Types
Supported Constants and Variables
String Handling
Supported Operators
Supported Class Features
Supported I/O with Kiwi
Data Structures with Kiwi 1/2
Data Structures with Kiwi 2/2 - more advanced and opaque temporary write up...
Dynamic Storage Allocation
Pointer Arithmetic
Garbage Collection
Testing Execution Env: Whether I am running on the Workstation, RTL_SIM or the FPGA blades.
Clone
Varargs
Delegates and Dynamic Free Variables
The ToString() Method
Accessing Numerical Value of Pointer Variables
Accessing Simulation Time
Run-time Status Monitoring, Waypoints and Exception Logging
Client versus Server Designs and Start Commands
Exiting Threads
Pause Modes (within Sequencer HLS Mode)
Unwound Loops
More-complex implied state machines
Inner loop unwound while outer loop not unwound.
Entry Point With Parameters
Generate Loop Unwinding: Code Articulation Point
Supported Libraries Cross Reference
System.Collections.Generic
Standard System.Math Library
Parallel For Loop
FU Redirects, Autoloads, Fenced IP and Swaps.
System.Random
Console.WriteLine and Console.Write
System.Threading.Barrier
get_ManagedThreadId
System.BitConverter
System.String.ToCharArray
System.IO.Path.Combine
TextWriter
TextReader
FileReader
FileWriter
Threading and Concurrency with Kiwi
Kiwi C# Attributes Cross Reference
Kiwi.Remote() Attribute
Asynchronous Invokation
Flag Unreachable Code
Hard and Soft Pause (Clock) Control
End Of Static Elaboration Marker - EndOfElaborate
Loop NoUnroll Manual Control
Elaborate/Subsume Manual Control
Synchronous and/or Asynchronous RAM Mapping
Register Widths and Overflow Wrapping
Net-level Input and Output Ports
Wide Net-level Inputs and Outputs
Clock Domains
Remote
Elaboration Pragmas - Kiwi.KPragma
Assertions Debug.Assert()
Assertions - Temporal Logic
RTL Parameters
Memories in Kiwi
On-chip RAM (and ROM) Mirror, Widen and Stripe Directives
ROMs (read-only memories) and Look-Up Tables
Forced Off-chip/Outboard Memory Array Mapping
Off-chip load/store ports
AXI and HFAST-to-AXI mapping
Off-chip address size
B-RAM Inference
Dual-port Block RAMs
Other multi-port RAMs
Substrate Gateway
Console I/O
Filesystem Interface
Hardware Server
Kiwi Performance Tuning
Kiwi Performance Predictor
Phase Changes, Waypoints and Code-point Markers
Growth Parameter Assertions/Denotations
Debug, Single Step and Directorate Interface
Spatially-Aware Binder
Generated RTL
RAM Library Blocks
ALU Library Blocks
Incremental Compilation and Black Boxes
IP Integration via IP-XACT
The Kiwi.Remote() Markup
Subsystem Abend Syndrome Routing
Design Examples
A get-started example: 32-bit counter.
Expert and Hardware-level User Guide
Kiwi Hard-Realtime Pipelined Accelerators
Pipelined Accelerator Example 1
Designing General/Reactive Hardware with Kiwi
Input and Output Ports
Register Widths and Wrapping
How to write state machines...
State Machines
Clock Domains
SystemCSharp
Kiwi Developers' Guide and Compiler Internal Operation
KiwiC Internal Operation
Background: HPR/LS Library (aka Orangepath)
DIC
ASM
RTL and FSM
CMD
Finite-State Machines
CSP/Occam
Internal Working of the KiwiC front end recipe stage
Miscellaneous
FAQ and Bugs
Orangepath Synthesis Engines
A* Live Path Interface Synthesiser
Transactor Synthesiser
Asynchronous Logic Synthesiser
SAT-based Logic Synthesiser
Bevelab: Synchronous FSM Synthesiser
Bevelab: Hard Pause Mode Internal Operation
Bevelab: Soft Pause Mode Internal Operation
VSFG - Value State Flow Graph
PSL Synthesiser
Statechart Synthesiser
SSMG Synthesiser
Repack Recipe Stage
Restructure Recipe Stage
Output and Analysis Recipe Stages
HPR Output Formats Supported
C++, SystemC and C# Output Generators
RTL Output Generator
IP-XACT Output Generator
Built-in report writers
Arithmetic and RAM Leaf Cells
Fixed-point ALUs
Floating-point ALUs
Floating-point Convertors
RAM and ROM Leaf Cells
HPR L/S (aka Orangepath) Facilities
FILES and DIRECTORIES
Recipe
Output Log and Report Files
Environment Variables and IncDir Search Paths
Espresso
Cone Refine
HPR Command Line Flags
Other output formats
General Command Line Flags
HPR L/S (aka Orangepath) FAQ
HPR System Integrator
Memory Map Management (Link Editing)
Deadlock and Combinational Paths
Constructive Placement
Multi-FPGA designs
Mux and Demux Blocks
Non-uniform Memory Access (NUMA)
Network On Chip (NoC)
Bus Definitions
Sewing Kit for Miscellaneous Nets
System Integrator Example Run
Diosim Simulator
Simulation Control Command Line Flags
Bibliography
Index
Index
David Greaves 2019-11-14