As mentioned before, the basic arm test is to exercise the processor part of the port controller. Given that the board might be broken and not have the capability to output anything on the serial line, the debug LED module is used to provide some information on the state of the tests. Given the minimal working hardware it should be possible to show on the LEDs in a recognised pattern if some of the following tests fail (in order of test):
If the board is working, then you should be seeing 0a, 10 and 17 on the LED display. The serial line test also send a '!' to the serial line. If all tests passed, you should then see "BASIC PROCESSOR TESTS PASSED" on the serial line. Notice that after this message, the Wanda micro-kernel would have started running and whole bunch of initialisation messages would have come up. Ignore these messages and wait until you are prompted to start the xiromtester.
If the hardware is broken, you would not drop into Wanda and the LED display will tell you the precise error (check with the table below). You might still get the '!' on the serial line depending on which stage of the tests the error crop up.
Make sure you power cycle the FPC if you want to repeat this test.
The LED display is used for both indicating the current state of the arm test as well as indicating the error state. The complete display code is as shown in Table 3:
You should only read this section if you want to know exactly what the tests are doing.
The arm test starts by getting into 32 bit data addressing mode follow by displaying '00' to indicate processor started. MEMC is then configured out of power on mode.
There is not much of the IOC that we can test without having external hardware working, but we can write and then read back the interrupt mask registers. This test is only safe if interrupts are disabled in the PSR mask (they are when the processor is reset).
By writing 0, 255 and 0x55 (alternate 1s and 0s) and reading each value back should reveal any dodgy data lines (data[0..7])
Check that LED lines are correct and that the transmission system is being held in reset, if OK then turn the LEDs on (but leave the transmission system in reset). The status of the LED lines and the Transmission reset line are available in the FIQ status register (though the bits are inverted from the logic level on the line)
Set up the keyboard and try to send a character. First try and read the clock-speed links, we expect them to be in a particular state and if not we barf. Next set the kart speed and reset the receiver. After resetting the receiver there should not be a pending receive. Reset the transmitter by sending the character '!'. After sending the character the transmission status should not be empty.
CRC is performed on the whole of ROM. The CRC check routine checks individual ROM chips, and should be called 4 times, one for each chip. On return, the zero flag is set if the result was zero.
Program MEMC for 4Mbytes of RAM. If we don't have 4M we loose. Have to do dummy writes to the address translation to set the mapping The page-address mapping is:
Only want 128 logical pages 
do the 16 (sensible) ones each time round inner loop, get low bits from table
This consists of several phases.
Things seems to be alright if reach here. Now boot the test software that is linked with a Wanda kernel: it is stored in the ROM immediately after this code. The first three words of a normal boot ROM are not executable at this offset, so we must skip over them.
