Basic Xilinx Test - Xiromtester

Xiromtester, the network part test is based on xi5tester. Xiromtester performs the following basic tests:

• Program Xilinx
• Re-program Xilinx
• Check data/irq lines from Xilinx to IOC
• SRAM test
• transmission Xilinx 3030 programming test.
• Podule test
• Loopback FIFO cell
• Transmission FIFO cell

All these tests are performed in the Wanda environment. After the processor tests have completed, Wanda is started. Xiromtester will automatically be invoked from Wanda kernel during boot. Xiromtester at this stage is configured in silent and auto-pilot mode. Tests are then carried out with minimum verbosity. During the silent mode test, only failed tests will be indicated on the console line. At the end of the test, a summary report will be shown to indicated the no. of tests failed or that all passed. After this, we enter an interactive mode xiromtester.

Do expect a small delay between finishing the basic test and any error/summary reports appears. An example of the test output looks like:

!BASIC PROCESSOR TESTS PASSED


Podule test                                     FAIL

        SUMMARY: 1 tests FAIL

Further Test and Debugging

If an error occurs, you will get error message indicating which test has failed. We would then be required to run the test in a more interactive way to find out about the precise error.

We can get into the interactive-mode by just pressing RETURN at where the tests stopped (as shown above). You will see this

TOP MENU

Choose tests from the following options:

1.      Xilinx basic Tests
2.      Xilinx xi5 bits Tests
x.      Exit Xilinx ROM Test

Choose 1 and you will get

XiRomTester Alive

xiromtester: MAIN MENU

Choose tests from the following options:

0.      Program Xi5 bits
1.      Program test1 bits
2.      Data/IRQ lines from Xilinx to IOC
3.      Test SRAM with fabric clock
4.      Transmission Xilinx Test
5.      Podule test
6.      Send Loopback Cells
7.      Send Tx Cells
t.      Interactive toggle
a.      All tests
e.      Execute selection
l.      Repeat Last (`` '')
x.      Exit xiromtester

To repeat all previous tests, choose option a and hit RETURN. You will see a whole bunch of messages indicating the setup of the tests. Ignore them for now. You then choose option e and hit RETURN. This will execute the tests and you should see something like:

Xi5 bits programming test               PASS
Test1 bits programming test             PASS
IRQ/IOC test                            PASS
SRAM test 30 iteration                  PASS
TXRX Test                               PASS
       ERROR: test podule: No test podule found
Podule test                                     FAIL
Fabric loop back test                   PASS
Transmission loop back test             PASS

Tests and Error Modes

Xilinx Programming

The first 2 tests in the list programmes the Xilinx with the two designs that we are going to use in our tests. If the Xilinx manage to program for the first time, there is a high likelihood that it will succeed the second time. Possible error conditions are:

1. Panic with "Xilinx INIT signal did not go inactive"
2. Panic with "HDC set, so re-program asserted INIT stays active"
3. Panic with "HDC signal was not asserted after re-program"
4. Panic with "Busy prior to configuration"

IRQ/IOC Check

This test aims to examine the integrity of the lines between Xilinx and IOC. If test 1 and 2 passed, the Xilinx programme data lines, INIT, HDC and BUSY should be intact. This test thus looks at the 3 FIQ and 2 IRQ conditions. The test1 xbits is used so that data written to Xilinx is made to appear on the IOC lines. By controlling the data written, different FIQ and IRQ conditions can be generated.

Possible error modes:

1. ERROR: Xilinx signal XXX does not happen

   Follow by information about the particular signal. This basically means no IRQ/FIQ has been seen.

2. ERROR: Xilinx signal XX causes wrong interrupt

   An interrupt has happened, but is not the one we expected. This is follow by information about the particular signal and a dump of what we think the current IOC status is.

SRAM Test

This test serves two purposes:

1. check address to Xilinx is intact for SRAM access
2. Given that Xilinx is the only device which drives the SRAM access, being able to read/write the SRAM correctly should imply the "slowarm" interface (using fabric clock) is OK. Xi5 bits is used here.

Possible error modes:

1. ERROR: at XXX (got YYY not ZZZ) again AAA

   Where XXX is the memory location, YYY is what we read back and ZZZ what we expected. AAA is another read retry.

2. ERRORS: XXX to YYY

   There are error from memory location XXX to YYY.

Transmission Xilinx Test

We want to verify that the transmission Xilinx has been programmed correctly. There is no easy way to deduce this. This test and the transmission FIFO loopback test should implicitly tell us the state of the programming.

We know that the transmission Xilinx generates a violation if we have transmission cable connected incorrectly or disconnected. Therefore if we have the loopback cable plug in, we should not see any violation.

Possible error mode:

1. ERROR: TXRX Test failed : Violations

   We still see violation when loopback cable is in. Something must be wrong. Check your connection and cable.

Podule Test

The Podule test tries to examine the integrity of lines to the Podule backplane. A simple Podule was constructed that allows us to first write the Podule and read it back for comparison. The test will search for the right Podule ID before the write/read. Therefore you can plug in any Podule slot on the backplane.

1. ERROR: test podule: error: XXX != YYY err=ZZZ

   The read back data YYY does not agree with data written XXX. err is the cumulative bit error (done using ORing all XOR of XXX and YYY). Using err we can then deduce what has gone wrong with the Table 4.

 
Table 4:   Podule Error Code

Cell loop back Test

The last two tests try to send a single cell to itself via the loop back FIFO and the transmission FIFO. This will exercise almost all parts in the network section of the FPC3 and therefore if the tests pass, we can declare the FPC3 to be in a sane state.

Possible error states are:

1. Cell Was NACKed This is the most likely error. One possible cause is when FPC3 is in the wrong slot (in technical term, we are using IFAB 5).
2. ERROR: Lost Cell
3. Free Q is empty
4. REMAP Error
5. Recv cell had XX errors:
6. after errors
7. Left slip
8. Right slip
9. Sent from word