psfig
Mark Hayter
16th February 1993
The Fairisle port controllers have a daughter board which contains the transmission system. The interface to the port controller is based around fifos to perform speed matching between the port controller and the network. A design has been done for a Xilinx 3020 programmable gate array for interfacing between the port controller and a TAXIchip driven line running the Fairisle/Yes/Maybe protocol. The version 3 port controllers (FPC3) have the transmission system on the main PCB, and have a revized control xilinx on a larger 3030 chip. The differences of the FPC3 version are described in the FPC3 Xilinx design document.
The organisation of the transmission card is shown in figure 1.
Figure 1: Fairisle TAXI Transmission Card