There is a version of the xilinx bits which has the transmission side of the system slowed. This is done by forcing the insertion of sync marks in the data stream, and only enabling transmission one byte time in n. The value of n is fixed by the xilinx, and to change it the lca has to be modified and the bits regenerated. This will allow experiments to be done with slow transmission lines without modification to the hardaware. The txrx chip on the FPC3 (described along with the main FPC3 xilinx chip) allows the slow speed to be changed under software control.