psfig
Mark Hayter and Richard Black
10th March 1994
The version 3 Fairisle Port Controller uses a xilinx 3090 as its main controller. This is substantially larger than the previous versions. Advantage has been taken of this to include many experimental and debugging aids in the device. The new design, the Xi5 bits, is based on the earlier Xi3 version with additions. The occasion was also exploited to make support of standard confirmant headers easier - in particular to present, and remap on contiguous VPI bits. The FPC3 also includes the transmission system on the main PCB, the improved txrx control chip forms the taxi5 design. This document describes the interface to these chips, and should be read along with the Xi3 and txrx chip descriptions.