Although the FIQ code for Xi5 is almost identical to Xi3, it was realised early in the design that a significant amount of work would be needed on the Wanda management code to use Xi5 correctly, and that that overhaul was already overdue. Unfortunately that work has not even begun. The current software is a set of horrible hacks that try and grunge the Xi5 device under the existing management code.
One problem is the fact that VCIs have a different value when
transmitted and received (due to the byte swap), including the Meta
Signalling VCI! The other is the lack of the local bit. This hasn't
even been fixed for local connections. Instead the software circulates
round half of the remap entries which are not used by normal remapping
(because Wanda still only supports 
connections not 
).
Amazingly enough this holds together well enough for some experiments to have taken place. From the performance point of view the FPC3 has been observed to be capable of the full line rate when FIFO queueing. Although there is never enough CPU left at this rate to run the operating system, the FIQ was observed to empty its work queue from time to time, indicating that it is not fully saturated.
More complex experiments have also taken place, but they will be detailed elsewhere.