Main xilinx changes

The Xi5 xilinx on the FPC3 is based on extensions to the Xi3 version on the FPC2. The queue management is identical, but the interupt and status details have changed. Externally the main changes are that the xilinx gets to see all of the SRAM data bus, allowing increases in sizes of timers and status information, and connections are made to the txrx chip to allow the CPU to monitor the state of the line.

Internal changes:

• Byte Swapping. When reading the header of an incomming cell, the Xi5 design swaps over the first two octets. In other words they are written in a big-endian format even though the rest of the cell is written in little-endian format. This ensures that the VPI bits in the standard header are contiguous in that word. Also it is these VPI bits that are used for referring to the cell buffers when performing remap operations.

• Source stamping The source information is now written to the same data bits as are used for the PT field in standard conformant headers. This means that a cell for Wanda (where the stamp is written to both the first two words) can be identified by checking the PT field. Hence no VPIs need be reserved for this purpose.

• Fifos. The FPC3 uses synchronous fifos and some changes must be made to enable the use these. In addition the xilinx will become responsible for resetting the fifos, both to ensure timing constraints are met and to allow separate resetting of them.

• Status. The status register will be increased in size to pass the extra information from the txrx chip. The report of line violations will be done using a count of the number of violations sine the last status clear. The counter will stop at all bits 1 to indicate overflow. There will also be an indication of the current violation state. If any of the latched status bits is set then an IRQ (maskable in IOC) is raised, and there is a separate IRQ for violations. If the receive fifo should become full through error this is also reported.

• Free running clock (FRC). The free running clock is increased to 16 bits, incremented every frame pulse. This count will continue to be readable by the processor and put in as the cell timestamp.

• Timer clock (TC). New to Xi5 this clock may be read and written by the processor. It will decrement every frame pulse and cause a FIQ on reaching zero. The FIQ is removed when TC is written with a new value - the IOC mask can be used to disable it at other times.

• Timestamping. The new xilinx can check the incomming VCI cells. The FDL specification has 16 bits in the VCI field, but the xilinx remap system only supports 11 bits. Three of the spare bits will, if non-zero, enable automatic timestamping into the data portion of the cell. The inbound VCI (which is used as the offset into the remap vector for cells going into the fabric) is used for determining the offset to place the timestamp in both incomming and outgoing cells. Table 1 indicates the mapping used - for convenience both the offset in the xilinx cell buffer and the offset in the data portion of the cell are shown. Clearly there is no synchronisation between port controllers, so the only meaningful thing to do is to compare measurements made on the same port controllers - though port controllers on the same fabric will increase at the same time. This function can be enabled and disabled by writing a command to the xilinx.

   
  Table 1:   Timestamp offsets
  

• Interrupts. The xilinx uses three IOC FIQ lines and two (edge sensitive) IRQ lines. All masking of interupts must be done by IOC.

• Local cells. The ``local'' bit in the transmit buffer address has been removed. All cells have their VCIs remapped going in to the fabric.

• Pass-on multicast. The portc route byte has been expanded by one bit. If set then a cell from the fabric is put into both transmit and loopback fifos (the cell is rejected if either is more than half full). This allows (probably with some VCI trickery) serial multicast by passing the cell on to another output. The portc route byte becomes:

   
  Table 2:   FPC3/Xi5 Port Controller Route byte