Research
My research focuses around extracting multiple forms of parallelism from applications through code transformations and architectural enhancements. Here I give an overview of some my current and previous work. See my research group page for details on my group, and my publications page for conference, journal and workshop papers.
A few years ago Arm published an article about our collaboration and, co-incidentally, the university also published a piece about the wider collaboration with Arm, of which I am a part.
With the advent of multi and many-core processors, there is a growing need for tools that can extract parallelism from general sequential codes. Automatic parallelisation is a seductive route to achieving this, since it removes the burden of identifying and exploiting parallelism from the programmer. However, automatically parallelising ordinary, irregular, single-threaded codes and obtaining significant speedups has historically been an extremely difficult challenge.
One of my early contributions in this direction has been on the HELIX parallelising compiler — a fully automatic, non-speculative loop parallelisation technique for generic sequential code. It identifies the most profitable loops to parallelise, taking account of the cross-iteration data dependences that they contain, as well as the amount of work that they perform. We developed the HELIX compiler and architectural support for fast communication between cores (a ring cache), achieving unrivalled speedups for non-numerical applications.
In recent years my group has developed Janus, a tool for automatic parallelisation of application binaries using a hybrid static-dynamic technique. Janus performs a static analysis of the program which it then passes to a dynamic binary modifier to alter the program on-the-fly at run time, gaining the benefits of both approaches.
LoopFrog is our latest approach. Here we restructure the program and add hints that indicate regions that may be parallel. The microarchitecture uses these to spin up threadlets internally that are transparent to the user and OS, and to track dependencies in case of violations. LoopFrog brings speculative multithreading to modern high-performance cores.
Key Publications
LoopFrog: In-Core Hint-Based Loop Parallelization
Márton Erdős, Utpal Bora, Akshay Bhosale, Bob Lytton, Ali Zaidi, Alexandra W. Chadwick, Yuxin Guo, Giacomo Gabrielli and Timothy M. Jones
International Symposium on Microarchitecture (MICRO), October 2025
Janus: Statically-Driven and Profile-Guided Automatic Dynamic Binary Parallelisation
Ruoyu Zhou and Timothy M. Jones
International Symposium on Code Generation and Optimization (CGO), February 2019
HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs
Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones, Gu-Yeon Wei and David Brooks
International Symposium on Computer Architecture (ISCA), June 2014
HELIX: Automatic Parallelization of Irregular Programs for Chip Multiprocessing
Simone Campanoni, Timothy M. Jones, Glenn Holloway, Vijay Janapa Reddi, Gu-Yeon Wei and David Brooks
International Symposium on Code Generation and Optimization (CGO), April 2012
Many modern workloads for high-performance compute (HPC) and data processing are heavily memory-latency bound, due to the von Neumann bottleneck in conventional multiprocessors. The traditional solution to overcome this has been prefetching: using hardware to detect common access patterns such as strides so as to bring the required data into fast cache memory before it is requested by the processor. However, existing techniques do not work well for irregular access patterns, as seen in linked data structures, and also in indirect memory accesses, where the addresses loaded are based on indices stored in arrays.
My group has developed both hardware and software schemes to aid in prefetching these indirect memory access patterns. Our event-triggered programmable hardware prefetcher runs small prefetch kernels extracted from the application to accurately fetch in upcoming data. Our software scheme targets any access pattern using an array for indirection, and is available as an open-source pass for LLVM.
Most recently we've looked again at runahead execution and have developed three schemes to vectorise these future instructions, taking advantage of the data-level parallelism in the processor to gain memory-level parallelism in prefetching. Vector runahead is our initial approach, decoupled vector runahead runs continuously rather than waiting for a full-window stall, and scalar vector runahead realises this scheme in a novel way for in-order cores.
Key Publications
Selected for IEEE Micro Top Picks from the Computer Architecture Conferences
Jaime Roelandts, Ajeya Naithani, Sam Ainsworth, Timothy M. Jones and Lieven Eeckhout
International Symposium on Microarchitecture (MICRO), November 2024
Best paper award winnerSelected for IEEE Micro Top Picks from the Computer Architecture Conferences
Ajeya Naithani, Jaime Roelandts, Sam Ainsworth, Timothy M. Jones and Lieven Eeckhout
International Symposium on Microarchitecture (MICRO), October 2023
Selected for IEEE Micro Top Picks from the Computer Architecture Conferences
Ajeya Naithani, Sam Ainsworth, Timothy M. Jones and Lieven Eeckhout
International Symposium on Computer Architecture (ISCA), June 2021
An Event-Triggered Programmable Prefetcher for Irregular Workloads
Sam Ainsworth and Timothy M. Jones
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2018
Software Prefetching for Indirect Memory Accesses
Sam Ainsworth and Timothy M. Jones
International Symposium on Code Generation and Optimization (CGO), February 2017
Modern day computer systems have benefited from being designed and manufactured using an ever-increasing budget of transistors with very reliable integrated circuits. However, moving forwards such a free lunch is over. As transistors shrink they become more susceptible to manufacturing variability, wearout and in-field faults, decreasing their reliability and shortening system lifespans.
We are tackling this challenge through both hardware and software schemes. Our work in DSN 2018 proposed a heterogeneous architecture to dramatically reduce the overheads of hardware error detection compared to industry-standard dual-core lockstep. COMET is a technique to improve the performance of multi-threaded reliability code that is inserted automatically by the compiler. ParaMedic provides hardware error correction on top of error detection, and ParaDox uses this to get performance gains or energy savings by overclocking the processor or undervolting it. Parallaft is a software-only error detection scheme, using heterogeneous cores to check the execution of an application with no need for recompilation or binary modification.
Key Publications
Parallaft: Runtime-based CPU Fault Tolerance via Heterogeneous Parallelism
Boyue Zhang, Sam Ainsworth, Lev Mukhanov and Timothy M. Jones
International Symposium on Code Generation and Optimization (CGO), March 2025
ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance
Sam Ainsworth, Lionel Zoubritzky, Alan Mycroft and Timothy M. Jones
International Symposium on High Performance Computer Architecture (HPCA), March 2021
ParaMedic: Heterogeneous Parallel Error Correction
Sam Ainsworth and Timothy M. Jones
International Conference on Dependable Systems and Networks (DSN), June 2019
Parallel Error Detection Using Heterogeneous Cores
Sam Ainsworth and Timothy M. Jones
International Conference on Dependable Systems and Networks (DSN), June 2018
COMET: Communication-Optimized Multi-threaded Error-detection Technique
Konstantina Mitropoulou, Vasileios Porpodas and Timothy M. Jones
International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2016
Security of computer systems and the data that they process has slowly been becoming more important. Then in January 2018 the disclosure of Spectre and Meltdown vulnerabilities rocketed security to a first-order design constraint.
We have done work to tackle a variety of security-related issues, from low-cost Spectre mitigations, to avoiding use-after-free vulnerabilities that manifest in C code (and other manually memory-managed languages) when programmers do not reason carefully enough about when memory should be freed. MuonTrap is a scheme to isolate speculative state within a small filter cache between the processor core and first level of the cache hierarchy, without introducing additional side channels that could leak information. The Guardian Council is a programmable solution for security monitoring, allowing operating-system-verified kernels to constantly check the execution of code running on a high-performance core. MineSweeper is a drop-in replacement for C's memory allocator, providing a quarantine facility when memory is freed in which to hold objects until we can be sure there are no dangling pointers to them.
Partnering with the team that developed CHERI, we have built CHERIvoke that leverages CHERI capabilities to provide fast pointer revocation. Furthermore, we've looked at how you can bring the benefits of these capabilities to accelerator systems that don't themselves have native capability support.
Key Publications
Adaptive CHERI Compartmentalization for Heterogeneous Accelerators
Jianyi Cheng, A. Theodore Markettos, Alexandre Joannou, Paul Metzger, Matthew Naylor, Peter Rugg and Timothy M. Jones
International Symposium on Computer Architecture (ISCA), June 2025
MineSweeper: A "Clean Sweep" for Drop-In Use-after-Free Prevention
Márton Erdős, Sam Ainsworth and Timothy M. Jones
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), February 2022
MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State
Sam Ainsworth and Timothy M. Jones
International Symposium on Computer Architecture (ISCA), June 2020
The Guardian Council: Parallel Programmable Hardware Security
Sam Ainsworth and Timothy M. Jones
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2020
CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety
Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel W. Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson and Timothy M. Jones
International Symposium on Microarchitecture (MICRO), October 2019
Single instruction multiple data (SIMD) instruction sets provide energy-efficient performance by taking advantage of data-level parallelism whereby each instruction is applied to a vector of data. In the past, my group has looked at schemes to increase the performance of SLP vectorisation, an algorithm to vectorise straight-line code (in contrast to vectorising loops). We achieved this by both adding extra, redundant instructions and by reducing the size of the graphs that the algorithm builds when identifying opportunities for vectorisation. We are now considering techniques to increase the coverage of vectorisation in general, through additional hardware and compiler support for it.
Key Publications
Speculative Vectorisation with Selective Replay
Peng Sun, Giacomo Gabrielli and Timothy M. Jones
International Symposium on Computer Architecture (ISCA), June 2021
Throttling Automatic Vectorization: When Less Is More
Vasileios Porpodas and Timothy M. Jones
International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2015
PSLP: Padded SLP Automatic Vectorization
Vasileios Porpodas, Alberto Magni and Timothy M. Jones
International Symposium on Code Generation and Optimization (CGO), February 2015
With the advent of multi and many-core processors, there is a growing need for tools that can extract parallelism from general sequential codes. Automatic parallelisation is a seductive route to achieving this, since it removes the burden of identifying and exploiting parallelism from the programmer. However, automatically parallelising ordinary, irregular, single-threaded codes and obtaining significant speedups has historically been an extremely difficult challenge.
One of my early contributions in this direction has been on the HELIX parallelising compiler — a fully automatic, non-speculative loop parallelisation technique for generic sequential code. It identifies the most profitable loops to parallelise, taking account of the cross-iteration data dependences that they contain, as well as the amount of work that they perform. We developed the HELIX compiler and architectural support for fast communication between cores (a ring cache), achieving unrivalled speedups for non-numerical applications.
In recent years my group has developed Janus, a tool for automatic parallelisation of application binaries using a hybrid static-dynamic technique. Janus performs a static analysis of the program which it then passes to a dynamic binary modifier to alter the program on-the-fly at run time, gaining the benefits of both approaches.
LoopFrog is our latest approach. Here we restructure the program and add hints that indicate regions that may be parallel. The microarchitecture uses these to spin up threadlets internally that are transparent to the user and OS, and to track dependencies in case of violations. LoopFrog brings speculative multithreading to modern high-performance cores.
Key Publications
LoopFrog: In-Core Hint-Based Loop Parallelization
Márton Erdős, Utpal Bora, Akshay Bhosale, Bob Lytton, Ali Zaidi, Alexandra W. Chadwick, Yuxin Guo, Giacomo Gabrielli and Timothy M. Jones
International Symposium on Microarchitecture (MICRO), October 2025
Janus: Statically-Driven and Profile-Guided Automatic Dynamic Binary Parallelisation
Ruoyu Zhou and Timothy M. Jones
International Symposium on Code Generation and Optimization (CGO), February 2019
HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs
Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones, Gu-Yeon Wei and David Brooks
International Symposium on Computer Architecture (ISCA), June 2014
HELIX: Automatic Parallelization of Irregular Programs for Chip Multiprocessing
Simone Campanoni, Timothy M. Jones, Glenn Holloway, Vijay Janapa Reddi, Gu-Yeon Wei and David Brooks
International Symposium on Code Generation and Optimization (CGO), April 2012
Many modern workloads for high-performance compute (HPC) and data processing are heavily memory-latency bound, due to the von Neumann bottleneck in conventional multiprocessors. The traditional solution to overcome this has been prefetching: using hardware to detect common access patterns such as strides so as to bring the required data into fast cache memory before it is requested by the processor. However, existing techniques do not work well for irregular access patterns, as seen in linked data structures, and also in indirect memory accesses, where the addresses loaded are based on indices stored in arrays.
My group has developed both hardware and software schemes to aid in prefetching these indirect memory access patterns. Our event-triggered programmable hardware prefetcher runs small prefetch kernels extracted from the application to accurately fetch in upcoming data. Our software scheme targets any access pattern using an array for indirection, and is available as an open-source pass for LLVM.
Most recently we've looked again at runahead execution and have developed three schemes to vectorise these future instructions, taking advantage of the data-level parallelism in the processor to gain memory-level parallelism in prefetching. Vector runahead is our initial approach, decoupled vector runahead runs continuously rather than waiting for a full-window stall, and scalar vector runahead realises this scheme in a novel way for in-order cores.
Key Publications
Selected for IEEE Micro Top Picks from the Computer Architecture Conferences
Jaime Roelandts, Ajeya Naithani, Sam Ainsworth, Timothy M. Jones and Lieven Eeckhout
International Symposium on Microarchitecture (MICRO), November 2024
Best paper award winnerSelected for IEEE Micro Top Picks from the Computer Architecture Conferences
Ajeya Naithani, Jaime Roelandts, Sam Ainsworth, Timothy M. Jones and Lieven Eeckhout
International Symposium on Microarchitecture (MICRO), October 2023
Selected for IEEE Micro Top Picks from the Computer Architecture Conferences
Ajeya Naithani, Sam Ainsworth, Timothy M. Jones and Lieven Eeckhout
International Symposium on Computer Architecture (ISCA), June 2021
An Event-Triggered Programmable Prefetcher for Irregular Workloads
Sam Ainsworth and Timothy M. Jones
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2018
Software Prefetching for Indirect Memory Accesses
Sam Ainsworth and Timothy M. Jones
International Symposium on Code Generation and Optimization (CGO), February 2017
Modern day computer systems have benefited from being designed and manufactured using an ever-increasing budget of transistors with very reliable integrated circuits. However, moving forwards such a free lunch is over. As transistors shrink they become more susceptible to manufacturing variability, wearout and in-field faults, decreasing their reliability and shortening system lifespans.
We are tackling this challenge through both hardware and software schemes. Our work in DSN 2018 proposed a heterogeneous architecture to dramatically reduce the overheads of hardware error detection compared to industry-standard dual-core lockstep. COMET is a technique to improve the performance of multi-threaded reliability code that is inserted automatically by the compiler. ParaMedic provides hardware error correction on top of error detection, and ParaDox uses this to get performance gains or energy savings by overclocking the processor or undervolting it. Parallaft is a software-only error detection scheme, using heterogeneous cores to check the execution of an application with no need for recompilation or binary modification.
Key Publications
Parallaft: Runtime-based CPU Fault Tolerance via Heterogeneous Parallelism
Boyue Zhang, Sam Ainsworth, Lev Mukhanov and Timothy M. Jones
International Symposium on Code Generation and Optimization (CGO), March 2025
ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance
Sam Ainsworth, Lionel Zoubritzky, Alan Mycroft and Timothy M. Jones
International Symposium on High Performance Computer Architecture (HPCA), March 2021
ParaMedic: Heterogeneous Parallel Error Correction
Sam Ainsworth and Timothy M. Jones
International Conference on Dependable Systems and Networks (DSN), June 2019
Parallel Error Detection Using Heterogeneous Cores
Sam Ainsworth and Timothy M. Jones
International Conference on Dependable Systems and Networks (DSN), June 2018
COMET: Communication-Optimized Multi-threaded Error-detection Technique
Konstantina Mitropoulou, Vasileios Porpodas and Timothy M. Jones
International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), October 2016
Security of computer systems and the data that they process has slowly been becoming more important. Then in January 2018 the disclosure of Spectre and Meltdown vulnerabilities rocketed security to a first-order design constraint.
We have done work to tackle a variety of security-related issues, from low-cost Spectre mitigations, to avoiding use-after-free vulnerabilities that manifest in C code (and other manually memory-managed languages) when programmers do not reason carefully enough about when memory should be freed. MuonTrap is a scheme to isolate speculative state within a small filter cache between the processor core and first level of the cache hierarchy, without introducing additional side channels that could leak information. The Guardian Council is a programmable solution for security monitoring, allowing operating-system-verified kernels to constantly check the execution of code running on a high-performance core. MineSweeper is a drop-in replacement for C's memory allocator, providing a quarantine facility when memory is freed in which to hold objects until we can be sure there are no dangling pointers to them.
Partnering with the team that developed CHERI, we have built CHERIvoke that leverages CHERI capabilities to provide fast pointer revocation. Furthermore, we've looked at how you can bring the benefits of these capabilities to accelerator systems that don't themselves have native capability support.
Key Publications
Adaptive CHERI Compartmentalization for Heterogeneous Accelerators
Jianyi Cheng, A. Theodore Markettos, Alexandre Joannou, Paul Metzger, Matthew Naylor, Peter Rugg and Timothy M. Jones
International Symposium on Computer Architecture (ISCA), June 2025
MineSweeper: A "Clean Sweep" for Drop-In Use-after-Free Prevention
Márton Erdős, Sam Ainsworth and Timothy M. Jones
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), February 2022
MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State
Sam Ainsworth and Timothy M. Jones
International Symposium on Computer Architecture (ISCA), June 2020
The Guardian Council: Parallel Programmable Hardware Security
Sam Ainsworth and Timothy M. Jones
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2020
CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety
Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel W. Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson and Timothy M. Jones
International Symposium on Microarchitecture (MICRO), October 2019
Single instruction multiple data (SIMD) instruction sets provide energy-efficient performance by taking advantage of data-level parallelism whereby each instruction is applied to a vector of data. In the past, my group has looked at schemes to increase the performance of SLP vectorisation, an algorithm to vectorise straight-line code (in contrast to vectorising loops). We achieved this by both adding extra, redundant instructions and by reducing the size of the graphs that the algorithm builds when identifying opportunities for vectorisation. We are now considering techniques to increase the coverage of vectorisation in general, through additional hardware and compiler support for it.
Key Publications
Speculative Vectorisation with Selective Replay
Peng Sun, Giacomo Gabrielli and Timothy M. Jones
International Symposium on Computer Architecture (ISCA), June 2021
Throttling Automatic Vectorization: When Less Is More
Vasileios Porpodas and Timothy M. Jones
International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2015
PSLP: Padded SLP Automatic Vectorization
Vasileios Porpodas, Alberto Magni and Timothy M. Jones
International Symposium on Code Generation and Optimization (CGO), February 2015