Used By

Subcells Used

Notes

A static logic 16-bit, 2 stage self-timed pipeline which can be wrapped into a ring (via buses at bottom of the data path slices). The data path is split into four 4-bit slices (contblock_v1 plus other cells). Chip wide input and output buses run vertically in metal 2. Power is via 2 fat metal 1 lines which are tapped off in metal 2 for the control and data path circuits. Wiring between the control and data blocks was performed automatically in an inefficient manner.

Key

	metal 2
	metal 1
	polysilicon
	via or contact
	N+
	P+
	N well