RAMs vary in their size and number of ports.
Single-ported SRAM is the most important and most simple resource. It connects to a bus as an addressable target. It is also used inside caches for tags and data.
Today's SoC designs have more than fifty percent of their silicon area devoted to SRAM for various purposes.
Commonly, synchronous RAMs are used, requiring typically one clock cycle of delay between address input and corresponding data output. The same address can be written with fresh data during the same clock cycle, if desired.
The illustrated RAM has a one clock cycle read latency. When a write occurs, the old value at the location is still read out, which is commonly a useful feature.
The `en' input signal is not striclty needed since the RAM could deliver read data on all cycles. However, this wastes power, so without an enable input we should ensure the address inputs are relatively stable when a RAM result is not needed.
Most RAMs in use on SoCs are synchronous with the data that is output being addressed the clock cycle before.
RAMs below a few hundred bits should typically be implemented as register files made of flip-flops.
RAMs for SoCs were originally supplied by specialist companies such as Virage and Artizan (although these are now part of larger EDA companies). A `RAM compiler' tool is run for each RAM in the SoC. It reads in the user's size, shape, access time and port definitions and creates a suite of models, including the physical data to be sent to the foundry.
High-density RAM (e.g. for L2 caches) may clock at half the main system clock rate and/or might need error correction logic to meet the system-wide reliability goal.
RAM consumes static and dynamic energy. The ESL section of these notes gives high-level modelling figures that include about 10 pJ per read or write operation and a leakage of 82 nW per bit.
| 12: (C) 2008-18, DJ Greaves, University of Cambridge, Computer Laboratory. |