SRAM Memories Continued.

On-chip SRAM needs a test mechanism. Various approaches:

Can test with software running on embedded processor.
Can have a special test mode, where address and data lines become directly controllable (JTAG or otherwise).
Can use a built-in hardware self test (BIST) wrapper that implements 0/F/5/A and walking ones typical tests.

Larger memories and specialised memories are normally off-chip for various reasons:

Large area: would not be cost-effective on-chip,
Specialised: proprietary or dense VLSI technology cannot best be made on a SoC die where the process is optimised for general logic,
Specialised: e.g. non-volatile process (such as FLASH)
Commodity parts: economies of scale (ZBT SRAM, DRAM, FLASH)

But in the last five years DRAM and FLASH have found their way onto the main SoC as maturing technology shifts the economic sweet spot.