CBG SoC Design Patterns and HLS Touchstones
Landing/Contents Page

SoC Design Patterns and HLS Touchstones

"Manual coding of hardware circuits is specialised and time-consuming. But the energy saved using custom hardware compared with conventional processing, whether for video compression on a mobile phone or weather forecasting in the cloud (sic), has become very attractive. Performance can also be much higher, especially for CPU-bound (i.e. not memory-bound or I/O-bound) applications, such as encryption and prime-number factoring. And for automated stock trading the achievable low-latency is another key benefit. So today, we see a number of drivers for taking easy-to-write software and mapping it to a hardware circuit. This process is generally called `High-level Synthesis' or HLS." - David J Greaves, 2017.

Portfolio Notes

  • SoC D&M Patterns Portfolio (PDF)

    SoC D&M Patterns by Subject

  • SP1 - SoC Parts

  • SP2 - Power and Energy

  • SP3 - Design Partition

  • SP4 - RTL

  • SP5 - Assertion-Based Design

  • SP6 - ESL - Electronic System Level Design

  • SP6b - Tools, Techniques, Engineering.

  • SP7 - High-level Synthesis

    HLS Notes only

  • High-Level Synthesis Slides (HTML)

  • High-Level Synthesis Notes (PDF)

    External Links

    HiPEAC 2013 A Fast and Stand-alone HLS Methodology for Hardware Accelerator Generation Under Resource Constraints Prost-Boucle, Muller, Rousseau.