ECAD & Architecture Workshop Two

Two Phase Signalling

Introduction

The objective of this practical is to design a delay line that is four seconds long. Use a push button on the board as input to your delay line and one of the seven segment displays as output. There should be a four second delay between a change in the state of the input button and that change appearing at the output. This is non-return-to-zero (NRZ) signalling (see ECAD lecture 3), also called two-phase signalling.

The Verilog Preprocessor

Since you will be changing bus widths in your code, you may find the preprocessor useful, so that the width of each bus can be defined in just one place in your verilog. This will mean that, when you come to change the bus widths, you do not need to search through to find all of the references.

For example, you can define a symbolic constant like this:

`define COUNTER_WIDTH 10

Note that the "`" is a back-tick, not an apostrophe. You can then define your bus like this:

wire [`COUNTER_WIDTH-1:0] q

which gives a 10-bit bus.

The Project Code

You should use two new modules:

• A Delay Module

  This will have the signature module delay( req, ack, clk );

  where req is the input, ack the output which follows the input with a four second delay, and clk is a 25.175MHz clock.

  For now just use the following code for this module:

  module delay( req, ack, clk );
  
    input  req;  // input request
    output ack;  // output acknowledge
    input  clk;  // clock
  
    reg    [`COUNTER_WIDTH-1:0] dly;
    reg    prev_req;
    reg    ack;
  
    always @(posedge clk) begin
      prev_req <= req;
  
      if(prev_req != req)
        dly <= -1;           // set delay to maximum value
      else if(dly != 0)
        dly <= dly-1;        // dly>0 so count down
  
      if(dly == 1)
        ack <= !ack;
    end
  
  endmodule
  

• The Top-Level Module

  This will have the signature

  module lab2( ck, request, leda, ledb );

  where ck is the 25.175 MHz clock, request is the input button and leda and ledb are the outputs to the seven segment displays required by the HexToLEDs.v module.

  The module will include both a delay module and a HexToLEDs module, as in the last lab. Make the seven segment display show a 0 if the output from the delay module is low or a 1 if it is high.

You will require the HexToLEDs.v file from the previous workshop.

Pin assignments

You haven't been given a .acf file for this workshop, so you'll have to make one yourself. In fact, the .acf file from the previous workshop will pretty much do, so download dice.acf to this week's project directory, and rename it to lab2.acf.

First open it using File | Open.... The first thing in the file (after Altera's copyright notice) is the assignments, but they are all for a chip called "dice". Our new chip is going to be called "lab2", so indicate this by changing CHIP dice to CHIP lab2.

Now close the .acf file. Make sure you have the right project name set, and open Assign | Pin/Location/Chip.... You'll need to rename the input from the push-button. To do this, select it from the list, and click Delete. Then type the new name (request) into Node Name, and the pin number (28) into Pin. Then click on Add, and then OK.

You should now be able to compile and program the chip.

Why doesn't it work?

• Are all of the pin assignments correct?
• Have you used the right programming file?
• Does it work in the simulator? Try turning on Setup/Hold to check setup & hold times, and using a clock of the right speed (~40ns).
• Try the timing analyser - this has this shortcut button: , and you want registered performance mode (). Click on Start, and it will tell you the maximum clock frequency for reliable operation of your circuit.

If you discover timing problems, you may need to break down your counter a bit - is it really necessary to clock it at 25MHz? Using the ARM's 24MHz clock will be considered to be cheating!

Questions

1. Why might timing problems occur?
2. Why is using a clock divider and clocking other parts of the circuit on its output not always a good idea?

Ticking Criteria

1. Your verilog code needs to be cleanly formatted and commented.
2. The verilog code must be strictly synchronous with all clocks coming from one of the two clock distribution networks. Derived clocks which are distributed over programmable wiring are dangerous because clock skew can vary widly.
3. You must give a live demonstration of your solution.
4. Answers to the questions for the lab must be added to the end of your code.
5. The following header must be added to all code submitted:

   //////////////////////////////////////////////////////////////////////////////
   // ECAD+Arch Workshop 2
   //
   // Your name
   // Your college
   // date
   //////////////////////////////////////////////////////////////////////////////