Lab 1 - Introduction to synthesis and simulation
To get you started we'll show you a viable work-flow though the Altera ECAD tools. These tools are full commercial-strength and are, therefore, quite complex, but fortunately we can safely ignore many of the options and features and yet still get useful work done.
This first lab itself contains two parts. The first part introduces the tPad board and Quartus; You will use Quartus to synthesise some SystemVerilog code you have written into a form which can used to program the Cyclone IV FPGA on the tPad. The second introduces Modelsim which will be used to simulate the TTC CPU discussed in lectures. You will write some assembler code to run on the TTC CPU during simulation.
Simulation is usually used extensively to test functional correctness of a design before embarking on timely synthesis runs. In Lab 2 you will do more simulation of the TTC before synthesising a multi-processor system for the tPad.
It is expected you will complete the first part in the first week and the second part in the second. This timing is a guideline, and many students decide to make a start on future parts of the lab at home to save themselves time when they are actually in the lab.