HOME
UP
  PREV
NEXT (Review/Revision of Verilog RTL)
Part II CST SoC D/M Slide Pack 1 (RTL)
Recommended Reading
Introduction: What is a SoC ?
Introduction: What is a SoC ?
Design Flow
Design Flow
Design Flow Diagram
Levels of Modelling Abstraction
Review/Revision of Verilog RTL
Review/Revision of Verilog RTL
RTL Summary View of Variant Forms.
Structural Verilog
Structure Flattening
2a/3: Continuous Assignment.
2b/3: Pure RTL : unordered register transfers.
Elementary Examples
3/3: Behavioural RTL
Simulation And Synthesis.
SRTL abstract syntax
Behavioural - `Non-Synthesisable' RTL
Structural Hazards.
Structural Hazards in RTL
Folding, Retiming & Recoding
Critical Paths
Transactional Handshaking in RTL
RTL Compared with Software
Further Synthesis Issues
RTL Conclusion