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SRTL abstract syntax

Abstract syntax for a synthesisable RTL (Verilog/VHDL) without provision for delays:

Expressions:

datatype ex_t =
    Num of int
  | Net of string
  | Inv of ex_t
  | Query of ex_t * ex_t * ex_t
  | Diadic of diop_t * ex_t * ex_t
  | Subscript of ex_t * ex_t

Imperative commands (might also include a 'case' statement) but no loops.

datatype cmd_t =
    Assign of ex_t * ex_t
  | If1 of ex_t * cmd_t
  | If2 of ex_t * cmd_t * cmd_t
  | Block of cmd_t list

Our top level will be an unordered list of the following sentences:

datatype s_t =
   Sequential of edge_t * ex_t * cmd_t
|  Combinational of ex_t * ex_t