Exercise on logical effort

Consider the design of a 6-input NOR function in CMOS. This could be implemented in several different ways:

• a single, static gate;
• a chain of logic consisting of a pair of 3-input NOR gates whose outputs are combined by a NAND gate followed by an inverter;
• a single, dynamic gate pulled up when φ=0 and evaluated when φ=1;
• a single, pseudo-nMOS gate.

Calculate the logical effort, parasitic delay and unitless delay for each of the four designs. Which is likely to be fastest?

What difference would it make if the gate were driving a large capacitative load?