Welcome to NetFPGA Summer Course 2015!
The course is open to researchers (graduate-students or postdocs) interested in developing new hardware-accelerated network applications, and academics, teaching classes using the NetFPGA-SUME platform. In this course you will learn about the NetFPGA platform, practice rapid prototyping of clean-slate devices and build a networking device. The 5-day summer course will be held at the Technion, IL.
The NetFPGA is an open platform enabling researchers and instructors to build high-performance, hardware-accelerated networking systems. The NetFPGA is the de-facto experimental platform for line-rate implementations of network research and it has a family of boards, supporting from 1GE to 100GE. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Protocol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.
By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to demonstrate rapid prototyping of networking devices, and the participants will design and implement a working project on top of the platform.
Background: This course is focused on the NetFPGA-SUME platform.Attendees will utilise a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required.
Dates: August 2nd-6th, 2015 (Sunday - Thursday)
Location: The Technion Computer Engineering Center, Fishbach Building, Technion City, 32000, Haifa, IL
The first two days of the course will provide basic knowledge in rapid prototyping using NetFPGA SUME. The next three days will combine a detailed look into development and implementation aspects, and developing a project over the NetFPGA SUME platform.
The following is a preliminary program
Day 1 (Sunday, August 2nd, 9.00 - 17.00)
Day 2 (Monday, August 3rd, 9.00 - 17.00)
Day 3 (Tuesday, August 4th, 9.00 - 17.00)
Day 4 (Wednesday, August 5th)
Day 5 (Thursday, August 6th, 9.00 - 17.00)
Short bio of our Tutors:
Noa Zilberman is a Research Associate at the University of Cambridge Computer Laboratory in England. Zilberman has over 15 years of industrial experience in the telecommunication and semiconductor industries. In her last role, Zilberman was a senior principal chip architect in Broadcom’s Network Switching group. Her research interests include open-source research using the NetFPGA platform, switching architectures, high speed interfaces, network measurements and Internet topology. Zilberman is a Senior Member of IEEE, a member of ACM and Usenix, and has a PhD in Electrical Engineering from Tel Aviv University.
Yury Audzevich is a Research Associate at the University of Cambridge Computer Laboratory in England. He is an expert on energy-efficient designs for high-bandwidth networking devices, and was the lead researcher of CONTEST (CONfigurable Transceiver Energy uSage Toolkit). Previously, he was an Alcatel-Lucent Research Associate at the University of Trento. His current research interests lie in the field of reconfigurable systems, circuit design and energy-efficiency aspects in communication architectures. Audzevich obtained his PhD in Information and Telecommunication technologies from the University of Trento.
Accommodation is available from many places in Haifa (TBD)
Prof. Mark Silberstein
Email: mark (AT) ee.technion.ac.il