FPGA virtualisation is also achievable using overlays. An overlay typically consists of an initialisation pattern for FPGA RAM that then behaves as ROM and which is served by a fixed design loaded into the rest of the configurable logic, regardless of the overlay selected.
Security is achieved in the same way that conventional O/S security is achieved: no direct/unchecked access to anything sensitive.
FPGA advantages: Massively parallel. No fetch/execute overhead.
FPGA problems: Inefficienct use of silicon area resulting in overly long nets. Too long to place and route. Overly supportive of bit-level operations.
A new generation of coarse-grain FPGA's is needed:
| 7: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory. |